00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------ 00019 -- Author : Martin Morlot 00020 -- Mail : martin.morlot@lpp.polytechnique.fr 00021 ------------------------------------------------------------------------------ 00022 library ieee; 00023 use ieee.std_logic_1164.all; 00024 library grlib; 00025 use grlib.amba.all; 00026 use grlib.stdlib.all; 00027 use grlib.devices.all; 00028 library lpp; 00029 use lpp.lpp_amba.all; 00030 use lpp.apb_devices_list.all; 00031 use lpp.lpp_fft.all; 00032 use lpp.lpp_memory.all; 00033 use work.fft_components.all; 00034 00036 00037 entity APB_FFT is 00038 generic ( 00039 pindex : integer := 0; 00040 paddr : integer := 0; 00041 pmask : integer := 16#fff#; 00042 pirq : integer := 0; 00043 abits : integer := 8; 00044 Data_sz : integer := 32; 00045 Addr_sz : integer := 8; 00046 addr_max_int : integer := 256); 00047 port ( 00048 clk : in std_logic; 00049 rst : in std_logic; 00050 apbi : in apb_slv_in_type; 00051 apbo : out apb_slv_out_type 00052 ); 00053 end APB_FFT; 00054 00055 00056 architecture ar_APB_FFT of APB_FFT is 00057 00058 signal ReadEnable : std_logic; 00059 signal WriteEnable : std_logic; 00060 signal FlagEmpty : std_logic; 00061 signal FlagFull : std_logic; 00062 signal DataIn_re : std_logic_vector(gWSIZE-1 downto 0); 00063 signal DataOut_re : std_logic_vector(gWSIZE-1 downto 0); 00064 signal DataIn_im : std_logic_vector(gWSIZE-1 downto 0); 00065 signal DataOut_im : std_logic_vector(gWSIZE-1 downto 0); 00066 signal DataIn : std_logic_vector(Data_sz-1 downto 0); 00067 signal DataOut : std_logic_vector(Data_sz-1 downto 0); 00068 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); 00069 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); 00070 00071 signal start : std_logic; 00072 signal load : std_logic; 00073 signal rdy : std_logic; 00074 00075 begin 00076 00077 APB : ApbDriver 00078 generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int) 00079 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); 00080 00081 00082 Extremum : Flag_Extremum 00083 port map(clk,rst,load,rdy,FlagFull,FlagEmpty); 00084 00085 00086 DEVICE : CoreFFT 00087 generic map( 00088 LOGPTS => gLOGPTS, 00089 LOGLOGPTS => gLOGLOGPTS, 00090 WSIZE => gWSIZE , 00091 TWIDTH => gTWIDTH , 00092 DWIDTH => gDWIDTH, 00093 TDWIDTH => gTDWIDTH , 00094 RND_MODE => gRND_MODE , 00095 SCALE_MODE => gSCALE_MODE, 00096 PTS => gPTS, 00097 HALFPTS => gHALFPTS , 00098 inBuf_RWDLY => gInBuf_RWDLY ) 00099 port map(clk,start,rst,WriteEnable,ReadEnable,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,rdy); 00100 00101 start <= not rst; 00102 00103 DataIn_re <= DataIn(31 downto 16); 00104 DataIn_im <= DataIn(15 downto 0); 00105 DataOut <= DataOut_re & DataOut_im; 00106 00107 end ar_APB_FFT;
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet