Design Unit List

Here is a list of all design unit members with links to the Entities and Packages they belong to:

entity	AD7688_drvr	AD7688 driver, generates all needed signal to drive this ADC
entity	AD7688_spi_if
entity	Adder
entity	ADDRcntr
entity	ADS7886_drvr
entity	ALU
package	amba_lcd_16x2_ctrlr
entity	AMBA_LCD_16x2_DRIVER
entity	APB_CNA	Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
entity	APB_FFT	Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
entity	APB_FIFO	Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
entity	APB_FifoRead	Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
entity	APB_FifoWrite	Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
entity	APB_IIR_CEL
entity	apb_lcd_ctrlr
entity	APB_MULTI_DIODE
entity	APB_SIMPLE_DIODE
entity	APB_UART
entity	ApbDriver	Driver APB "Générique" qui va faire le lien entre le bus Amba et la FIFO
architecture	ar_AD7688_drvr
architecture	ar_AD7688_spi_if
architecture	ar_Adder
architecture	ar_ADDRcntr
architecture	ar_ADS7886_drvr
architecture	ar_ALU
architecture	ar_APB_CNA
architecture	ar_APB_FFT
architecture	ar_APB_FIFO
architecture	ar_APB_FifoRead
architecture	ar_APB_FifoWrite
architecture	AR_APB_IIR_CEL
architecture	AR_APB_MULTI_DIODE
architecture	AR_APB_SIMPLE_DIODE
architecture	ar_APB_UART
architecture	ar_ApbDriver
architecture	ar_BaudGen
architecture	ar_Clk_divider
architecture	ar_CNA_TabloC
architecture	ar_Fifo_Read
architecture	ar_Fifo_Write
architecture	ar_FILTER
architecture	ar_FILTER_RAM_CTRLR
architecture	ar_FilterCTRLR
architecture	ar_Flag_Extremum
architecture	ar_Gene_SYNC
architecture	ar_IIR_CEL_CTRLR
architecture	ar_IIR_CEL_FILTER
architecture	ar_LCD_16x2_ENGINE
architecture	ar_LCD_CLK_GENERATOR
architecture	ar_Link_Reg
architecture	ar_lpp_apb_ad_conv
architecture	ar_MAC
architecture	ar_MAC_CONTROLER
architecture	ar_MAC_MUX
architecture	ar_MAC_MUX2
architecture	ar_MAC_REG
architecture	ar_Multiplier
architecture	ar_MUX2
architecture	ar_RAM_CEL
architecture	ar_RAM_CTRLR2
architecture	ar_REG
architecture	ar_RShifter
architecture	ar_Serialize
architecture	ar_Shift_REG
architecture	ar_Systeme_Clock
architecture	ar_TestbenshALU
architecture	ar_TestbenshMAC
architecture	ar_Top_FIFO
architecture	ar_Top_FifoRead
architecture	ar_Top_FifoWrite
architecture	ar_UART
entity	BaudGen	This is an automatic Baud generator. To synchronize baudrate, it measure the smalest time between two transitions of RXD. So to set baud rate, the device connected to this UART should send at least one data such as 0xA5 (0b10100101) witch gives a lot of transition of one bit length
architecture	Behavioral
architecture	Behavioral
architecture	Behavioral
architecture	Behavioral
architecture	Behavioral
entity	Clk_divider
entity	CNA_TabloC	Programme du Convertisseur Numérique/Analogique
package	Convertisseur_config
architecture	DEF_ARCH
entity	Fifo_Read	Programme de la FIFO de lecture
entity	Fifo_Write	Programme de la FIFO d'écriture
entity	FILTER
entity	FILTER_RAM_CTRLR
package	FILTERcfg
entity	FilterCTRLR
entity	Flag_Extremum	Programme qui va permettre de générer des flags utilisés au niveau du driver C
entity	FRAME_CLK_GEN
entity	Gene_SYNC	Programme qui va permettre de générer le signal SYNC
package	general_purpose
entity	IIR_CEL_CTRLR
entity	IIR_CEL_FILTER
package	iir_filter
package	LCD_16x2_CFG
entity	LCD_16x2_DRIVER
entity	LCD_16x2_ENGINE
entity	LCD_2x16_DRIVER
entity	LCD_CLK_GENERATOR
entity	Link_Reg	Programme qui va permettre de "pipeliner" la FIFO, donnée disponible en sortie dé son écriture en entrée de la FIFO
package	lpp_ad_conv
package	lpp_amba
entity	lpp_apb_ad_conv
package	lpp_cna	Package contenant tous les programmes qui forment le composant intégré dans le léon
package	lpp_fft	Package contenant tous les programmes qui forment le composant intégré dans le léon
package	lpp_memory	Package contenant tous les programmes qui forment le composant intégré dans le léon
package	lpp_uart
entity	MAC
entity	MAC_CONTROLER
entity	MAC_MUX
entity	MAC_MUX2
entity	MAC_REG
entity	Multiplier
entity	MUX2
entity	RAM
entity	RAM_CEL
entity	RAM_CTRLR2
entity	REG
entity	RShifter
entity	Serialize	Programme qui permet de sérialiser un vecteur
entity	Shift_REG	Universal shift register can be used to serialize or deserialize data
entity	Systeme_Clock	Programme qui va permetre de générer l'horloge systeme (sclk)
entity	TestbenshALU
entity	TestbenshMAC
entity	Top_FIFO	Programme de la FIFO
entity	Top_FifoRead	Programme de la FIFO
entity	Top_FifoWrite	Programme de la FIFO
entity	UART	A general purpose UART with automatic baudrate