00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ------------------------------------------------------------------------------- 00022 library IEEE; 00023 use IEEE.STD_LOGIC_1164.ALL; 00024 use IEEE.NUMERIC_STD.ALL; 00025 library lpp; 00026 use lpp.amba_lcd_16x2_ctrlr.all; 00027 00028 entity FRAME_CLK_GEN is 00029 generic(OSC_freqKHz : integer := 50000); 00030 Port ( clk : in STD_LOGIC; 00031 reset : in STD_LOGIC; 00032 FRAME_CLK : out STD_LOGIC); 00033 end FRAME_CLK_GEN; 00034 00035 architecture Behavioral of FRAME_CLK_GEN is 00036 00037 Constant Goal_FRAME_CLK_FREQ : integer := 25; 00038 00039 Constant FRAME_CLK_TRIG : integer := OSC_freqKHz*500/Goal_FRAME_CLK_FREQ -1; 00040 00041 signal CPT : integer := 0; 00042 signal FRAME_CLK_reg : std_logic :='0'; 00043 00044 begin 00045 00046 FRAME_CLK <= FRAME_CLK_reg; 00047 00048 process(reset,clk) 00049 begin 00050 if reset = '0' then 00051 CPT <= 0; 00052 FRAME_CLK_reg <= '0'; 00053 elsif clk'event and clk = '1' then 00054 if CPT = FRAME_CLK_TRIG then 00055 CPT <= 0; 00056 FRAME_CLK_reg <= not FRAME_CLK_reg; 00057 else 00058 CPT <= CPT + 1; 00059 end if; 00060 end if; 00061 end process; 00062 end Behavioral; 00063 00064 00065 00066 00067 00068 00069 00070 00071
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet