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dsp/lpp_fft/Flag_Extremum.vhd

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00001 ------------------------------------------------------------------------------
00002 --  This file is a part of the LPP VHDL IP LIBRARY
00003 --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
00004 --
00005 --  This program is free software; you can redistribute it and/or modify
00006 --  it under the terms of the GNU General Public License as published by
00007 --  the Free Software Foundation; either version 3 of the License, or
00008 --  (at your option) any later version.
00009 --
00010 --  This program is distributed in the hope that it will be useful,
00011 --  but WITHOUT ANY WARRANTY; without even the implied warranty of
00012 --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00013 --  GNU General Public License for more details.
00014 --
00015 --  You should have received a copy of the GNU General Public License
00016 --  along with this program; if not, write to the Free Software
00017 --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
00018 ------------------------------------------------------------------------------
00019 --                        Author : Martin Morlot
00020 --                     Mail : martin.morlot@lpp.polytechnique.fr
00021 ------------------------------------------------------------------------------
00022 library IEEE;
00023 use IEEE.std_logic_1164.all;
00024 use IEEE.numeric_std.all;
00025 use work.FFT_config.all;
00026 
00028 
00029 entity Flag_Extremum is
00030   port(
00031     clk,raz    : in std_logic;
00032     load       : in std_logic;
00033     y_rdy      : in std_logic;
00034     full       : out std_logic;
00035     empty      : out std_logic
00036     );
00037 end Flag_Extremum;
00038 
00040 
00041 architecture ar_Flag_Extremum of Flag_Extremum is
00042 
00043 begin
00044     process (clk,raz)
00045     begin
00046         if(raz='0')then
00047             full  <= '1';
00048             empty <= '1';            
00049 
00050         elsif(clk' event and clk='1')then
00051 
00052             if(load='1' and y_rdy='0')then
00053                 full  <= '0';
00054                 empty <= '1';
00055             
00056             elsif(y_rdy='1')then
00057                 full  <= '1';
00058                 empty <= '0';
00059 
00060             else
00061                 full  <= '1';
00062                 empty <= '1';
00063 
00064             end if;
00065         end if;
00066     end process;
00067 
00068 end ar_Flag_Extremum;
00069 
00070                 
00071 
00072 

© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet