00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ---------------------------------------------------------------------------- 00022 library IEEE; 00023 use IEEE.STD_LOGIC_1164.ALL; 00024 library lpp; 00025 use lpp.lpp_ad_conv.all; 00026 use lpp.general_purpose.Clk_divider; 00027 00028 entity AD7688_spi_if is 00029 generic(ChanelCount : integer); 00030 Port( clk : in STD_LOGIC; 00031 reset : in STD_LOGIC; 00032 cnv : in STD_LOGIC; 00033 DataReady: out std_logic; 00034 sdi : in AD7688_in(ChanelCount-1 downto 0); 00035 smpout : out Samples_out(ChanelCount-1 downto 0) 00036 ); 00037 end AD7688_spi_if; 00038 00039 architecture ar_AD7688_spi_if of AD7688_spi_if is 00040 00041 signal shift_reg : Samples_out(ChanelCount-1 downto 0); 00042 signal i : integer range 0 to 15 :=0; 00043 signal cnv_reg : std_logic := '0'; 00044 00045 begin 00046 00047 00048 00049 process(clk,reset) 00050 begin 00051 if reset = '0' then 00052 for l in 0 to ChanelCount-1 loop 00053 shift_reg(l) <= (others => '0'); 00054 end loop; 00055 i <= 0; 00056 cnv_reg <= '0'; 00057 elsif clk'event and clk = '1' then 00058 if cnv = '0' and cnv_reg = '0' then 00059 if i = 15 then 00060 i <= 0; 00061 cnv_reg <= '1'; 00062 else 00063 DataReady <= '0'; 00064 i <= i+1; 00065 for l in 0 to ChanelCount-1 loop 00066 shift_reg(l)(0) <= sdi(l).SDI; 00067 shift_reg(l)(15 downto 1) <= shift_reg(l)(14 downto 0); 00068 end loop; 00069 end if; 00070 else 00071 cnv_reg <= not cnv; 00072 smpout <= shift_reg; 00073 DataReady <= '1'; 00074 end if; 00075 end if; 00076 end process; 00077 00078 end ar_AD7688_spi_if;
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet