general_purpose/ADDRcntr.vhd

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------------------------------------------------------------------------------
--  This file is a part of the LPP VHDL IP LIBRARY
--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
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--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License as published by
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-------------------------------------------------------------------------------
--                    Author : Alexis Jeandet
--                     Mail : alexis.jeandet@lpp.polytechnique.fr
----------------------------------------------------------------------------
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
library lpp;
use lpp.general_purpose.all;



entity ADDRcntr is 
port(
    clk     :   in  std_logic;
    reset   :   in  std_logic;
    count   :   in  std_logic;
    clr     :   in  std_logic;
    Q       :   out std_logic_vector(7 downto 0)
);
end entity;




architecture ar_ADDRcntr of ADDRcntr is

signal  reg :   std_logic_vector(7 downto 0);

begin

Q   <=  REG;

process(clk,reset)
begin
if reset = '0' then
    REG     <=  (others => '0');
elsif clk'event and clk ='1' then
    if clr = '1' then
        REG <=  (others => '0');
    elsif count ='1' then
        REG <=  std_logic_vector(unsigned(REG)+1);
    end if;
end if;
end process;

end ar_ADDRcntr;