Inherits Adder::ar_Adder.
Inherited by general_purpose [private], and ar_MAC.
Architectures | |
| ar_Adder | Architecture |
Libraries | |
| IEEE | |
| lpp | |
Packages | |
| numeric_std | |
| std_logic_1164 | |
| general_purpose | Package <general_purpose> |
Generics | |
| Input_SZ_A | integer := 16 |
| Input_SZ_B | integer := 16 |
Ports | |
| clk | in std_logic |
| reset | in std_logic |
| clr | in std_logic |
| add | in std_logic |
| OP1 | in std_logic_vector ( Input_SZ_A -1 downto 0 ) |
| OP2 | in std_logic_vector ( Input_SZ_B -1 downto 0 ) |
| RES | out std_logic_vector ( Input_SZ_A -1 downto 0 ) |
Definition at line 30 of file Adder.vhd.
general_purpose package [Package] |
Input_SZ_A integer := 16 [Generic] |
Input_SZ_B integer := 16 [Generic] |
numeric_std package [Package] |
OP1 in std_logic_vector ( Input_SZ_A -1 downto 0 ) [Port] |
OP2 in std_logic_vector ( Input_SZ_B -1 downto 0 ) [Port] |
RES out std_logic_vector ( Input_SZ_A -1 downto 0 ) [Port] |
std_logic_1164 package [Package] |