00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------ 00019 -- Author : Martin Morlot 00020 -- Mail : martin.morlot@lpp.polytechnique.fr 00021 ------------------------------------------------------------------------------ 00022 library ieee; 00023 use ieee.std_logic_1164.all; 00024 library grlib; 00025 use grlib.amba.all; 00026 use grlib.stdlib.all; 00027 use grlib.devices.all; 00028 library lpp; 00029 use lpp.lpp_amba.all; 00030 use lpp.apb_devices_list.all; 00031 use lpp.lpp_memory.all; 00032 00034 00035 entity APB_FIFO is 00036 generic ( 00037 pindex : integer := 0; 00038 paddr : integer := 0; 00039 pmask : integer := 16#fff#; 00040 pirq : integer := 0; 00041 abits : integer := 8; 00042 Data_sz : integer := 16; 00043 Addr_sz : integer := 8; 00044 addr_max_int : integer := 256); 00045 port ( 00046 clk : in std_logic; 00047 rst : in std_logic; 00048 apbi : in apb_slv_in_type; 00049 apbo : out apb_slv_out_type 00050 ); 00051 end APB_FIFO; 00052 00053 00054 architecture ar_APB_FIFO of APB_FIFO is 00055 00056 signal ReadEnable : std_logic; 00057 signal WriteEnable : std_logic; 00058 signal FlagEmpty : std_logic; 00059 signal FlagFull : std_logic; 00060 signal DataIn : std_logic_vector(Data_sz-1 downto 0); 00061 signal DataOut : std_logic_vector(Data_sz-1 downto 0); 00062 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); 00063 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); 00064 00065 begin 00066 00067 APB : ApbDriver 00068 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) 00069 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); 00070 00071 00072 DEVICE : Top_FIFO 00073 generic map(Data_sz,Addr_sz,addr_max_int) 00074 port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); 00075 00076 00077 end ar_APB_FIFO;
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet