00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ------------------------------------------------------------------------------- 00022 library IEEE; 00023 use IEEE.numeric_std.all; 00024 use IEEE.std_logic_1164.all; 00025 library lpp; 00026 use lpp.iir_filter.all; 00027 use lpp.FILTERcfg.all; 00028 use lpp.general_purpose.all; 00029 --Maximum filter speed(smps/s) = Fclk/(Nchanels*Ncoefs) 00030 --exemple 26MHz sys clock and 6 chanels @ 110ksmps/s 00031 --Ncoefs = 26 000 000 /(6 * 110 000) = 39 coefs 00032 00033 entity FILTER is 00034 generic(Smpl_SZ : integer := 16; 00035 ChanelsCNT : integer := 3 00036 ); 00037 port( 00038 00039 reset : in std_logic; 00040 clk : in std_logic; 00041 sample_clk : in std_logic; 00042 Sample_IN : in std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0); 00043 Sample_OUT : out std_logic_vector(Smpl_SZ*ChanelsCNT-1 downto 0) 00044 ); 00045 end entity; 00046 00047 00048 00049 00050 00051 architecture ar_FILTER of FILTER is 00052 00053 00054 00055 00056 signal ALU_ctrl : std_logic_vector(3 downto 0); 00057 signal Sample : std_logic_vector(Smpl_SZ-1 downto 0); 00058 signal Coef : std_logic_vector(Coef_SZ-1 downto 0); 00059 signal ALU_OUT : std_logic_vector(Smpl_SZ+Coef_SZ-1 downto 0); 00060 00061 begin 00062 00063 --============================================================== 00064 --=========================A L U================================ 00065 --============================================================== 00066 ALU1 : entity ALU 00067 generic map( 00068 Arith_en => 1, 00069 Logic_en => 0, 00070 Input_SZ_1 => Smpl_SZ , 00071 Input_SZ_2 => Coef_SZ 00072 00073 ) 00074 port map( 00075 clk => clk, 00076 reset => reset , 00077 ctrl => ALU_ctrl , 00078 OP1 => Sample , 00079 OP2 => Coef, 00080 RES => ALU_OUT 00081 ); 00082 --============================================================== 00083 00084 --============================================================== 00085 --===============F I L T E R C O N T R O L E R================ 00086 --============================================================== 00087 filterctrlr1 : FilterCTRLR 00088 port map( 00089 reset => reset, 00090 clk => clk, 00091 sample_clk => sample_clk, 00092 ALU_Ctrl => ALU_ctrl , 00093 sample_in => sample_Tbl , 00094 coef => Coef, 00095 sample => Sample 00096 ); 00097 --============================================================== 00098 00099 chanelCut : for i in 0 to ChanelsCNT-1 generate 00100 sample_Tbl(i) <= Sample_IN((i+1)*Smpl_SZ-1 downto i*Smpl_SZ); 00101 end generate; 00102 00103 00104 00105 00106 end ar_FILTER; 00107
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet