Inherits ALU::ar_ALU.
Inherited by ar_FILTER, general_purpose [private], ar_IIR_CEL_CTRLR, and ar_TestbenshALU.
Architectures | |
| ar_ALU | Architecture |
Libraries | |
| IEEE | |
| lpp | |
Packages | |
| numeric_std | |
| std_logic_1164 | |
| general_purpose | Package <general_purpose> |
Generics | |
| Arith_en | integer := 1 |
| Logic_en | integer := 1 |
| Input_SZ_1 | integer := 16 |
| Input_SZ_2 | integer := 9 |
Ports | |
| clk | in std_logic |
| reset | in std_logic |
| ctrl | in std_logic_vector ( 3 downto 0 ) |
| OP1 | in std_logic_vector ( Input_SZ_1 -1 downto 0 ) |
| OP2 | in std_logic_vector ( Input_SZ_2 -1 downto 0 ) |
| RES | out std_logic_vector ( Input_SZ_1 +Input_SZ_2 -1 downto 0 ) |
Definition at line 31 of file ALU.vhd.
clk in std_logic [Port] |
Reimplemented from MAC.
Reimplemented in APB_IIR_CEL, IIR_CEL_CTRLR, IIR_CEL_FILTER, and ar_TestbenshALU.
ctrl in std_logic_vector ( 3 downto 0 ) [Port] |
Reimplemented in ar_TestbenshALU.
general_purpose package [Package] |
Reimplemented from MAC.
Reimplemented in APB_IIR_CEL, IIR_CEL_CTRLR, and IIR_CEL_FILTER.
IEEE library [Library] |
Reimplemented from MAC.
Reimplemented in IIR_CEL_CTRLR, IIR_CEL_FILTER, and TestbenshALU.
Input_SZ_1 integer := 16 [Generic] |
Input_SZ_2 integer := 9 [Generic] |
lpp library [Library] |
Reimplemented from MAC.
Reimplemented in APB_IIR_CEL, IIR_CEL_CTRLR, and IIR_CEL_FILTER.
numeric_std package [Package] |
Reimplemented from MAC.
Reimplemented in APB_IIR_CEL, IIR_CEL_CTRLR, IIR_CEL_FILTER, and TestbenshALU.
OP1 in std_logic_vector ( Input_SZ_1 -1 downto 0 ) [Port] |
OP2 in std_logic_vector ( Input_SZ_2 -1 downto 0 ) [Port] |
RES out std_logic_vector ( Input_SZ_1 +Input_SZ_2 -1 downto 0 ) [Port] |
reset in std_logic [Port] |
Reimplemented from MAC.
Reimplemented in IIR_CEL_CTRLR, IIR_CEL_FILTER, and ar_TestbenshALU.
std_logic_1164 package [Package] |
Reimplemented from MAC.
Reimplemented in APB_IIR_CEL, IIR_CEL_CTRLR, IIR_CEL_FILTER, and TestbenshALU.