00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------ 00019 -- Author : Martin Morlot 00020 -- Mail : martin.morlot@lpp.polytechnique.fr 00021 ------------------------------------------------------------------------------ 00022 library IEEE; 00023 use IEEE.std_logic_1164.all; 00024 use IEEE.numeric_std.all; 00025 00027 00028 entity Fifo_Read is 00029 generic( 00030 Addr_sz : integer := 8; 00031 addr_max_int : integer := 256); 00032 port( 00033 clk,raz : in std_logic; 00034 flag_RE : in std_logic; 00035 Waddr : in std_logic_vector(addr_sz-1 downto 0); 00036 empty : out std_logic; 00037 Raddr : out std_logic_vector(addr_sz-1 downto 0) 00038 ); 00039 end Fifo_Read; 00040 00042 00043 architecture ar_Fifo_Read of Fifo_Read is 00044 00045 signal Rad_int : integer range 0 to addr_max_int; 00046 signal Rad_int_reg : integer range 0 to addr_max_int; 00047 signal Wad_int : integer range 0 to addr_max_int; 00048 signal Wad_int_reg : integer range 0 to addr_max_int; 00049 signal flag_reg : std_logic; 00050 00051 begin 00052 process (clk,raz) 00053 begin 00054 if(raz='0')then 00055 Rad_int <= 0; 00056 empty <= '1'; 00057 00058 elsif(clk' event and clk='1')then 00059 Wad_int_reg <= Wad_int; 00060 Rad_int_reg <= Rad_int; 00061 flag_reg <= flag_RE; 00062 00063 if(flag_reg ='0' and flag_RE='1')then 00064 if(Rad_int=addr_max_int-1)then 00065 Rad_int <= 0; 00066 else 00067 Rad_int <= Rad_int+1; 00068 end if; 00069 end if; 00070 00071 if(Rad_int_reg /= Rad_int)then 00072 if(Rad_int=Wad_int)then 00073 empty <= '1'; 00074 else 00075 empty <= '0'; 00076 end if; 00077 elsif(Wad_int_reg /= Wad_int)then 00078 empty <= '0'; 00079 end if; 00080 end if; 00081 end process; 00082 00083 Wad_int <= to_integer(unsigned(Waddr)); 00084 Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz)); 00085 00086 end ar_Fifo_Read;
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet