ar_Fifo_Read Architecture Reference

Inherited by Fifo_Read.

List of all members.



Processes

PROCESS_33  ( clk , raz )

Signals

Rad_int  integer range 0 to addr_max_int
Rad_int_reg  integer range 0 to addr_max_int
Wad_int  integer range 0 to addr_max_int
Wad_int_reg  integer range 0 to addr_max_int
flag_reg  std_logic

Detailed Description

En aval de la SRAM Gaisler

Definition at line 43 of file Fifo_Read.vhd.


Member Function Documentation

[Process]
PROCESS_33 ( clk ,
raz )

Definition at line 52 of file Fifo_Read.vhd.


Member Data Documentation

flag_reg std_logic [Signal]

Definition at line 49 of file Fifo_Read.vhd.

Rad_int integer range 0 to addr_max_int [Signal]

Definition at line 45 of file Fifo_Read.vhd.

Rad_int_reg integer range 0 to addr_max_int [Signal]

Definition at line 46 of file Fifo_Read.vhd.

Wad_int integer range 0 to addr_max_int [Signal]

Definition at line 47 of file Fifo_Read.vhd.

Wad_int_reg integer range 0 to addr_max_int [Signal]

Definition at line 48 of file Fifo_Read.vhd.


The documentation for this class was generated from the following file: