00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ---------------------------------------------------------------------------- 00022 library IEEE; 00023 use IEEE.numeric_std.all; 00024 use IEEE.std_logic_1164.all; 00025 library lpp; 00026 use lpp.general_purpose.all; 00027 00028 00029 00030 entity MAC_MUX is 00031 generic( 00032 Input_SZ_A : integer := 16; 00033 Input_SZ_B : integer := 16 00034 00035 ); 00036 port( 00037 sel : in std_logic; 00038 INA1 : in std_logic_vector(Input_SZ_A-1 downto 0); 00039 INA2 : in std_logic_vector(Input_SZ_A-1 downto 0); 00040 INB1 : in std_logic_vector(Input_SZ_B-1 downto 0); 00041 INB2 : in std_logic_vector(Input_SZ_B-1 downto 0); 00042 OUTA : out std_logic_vector(Input_SZ_A-1 downto 0); 00043 OUTB : out std_logic_vector(Input_SZ_B-1 downto 0) 00044 ); 00045 end entity; 00046 00047 00048 00049 00050 architecture ar_MAC_MUX of MAC_MUX is 00051 00052 begin 00053 00054 OUTA <= INA1 when sel = '0' else INA2; 00055 OUTB <= INB1 when sel = '0' else INB2; 00056 00057 end ar_MAC_MUX;
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet