00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ---------------------------------------------------------------------------- 00022 library ieee; 00023 use ieee.std_logic_1164.all; 00024 use IEEE.numeric_std.all; 00025 00026 entity RAM_CEL is 00027 port( WD : in std_logic_vector(35 downto 0); RD : out 00028 std_logic_vector(35 downto 0);WEN, REN : in std_logic; 00029 WADDR : in std_logic_vector(7 downto 0); RADDR : in 00030 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic 00031 ) ; 00032 end RAM_CEL; 00033 00034 00035 00036 architecture ar_RAM_CEL of RAM_CEL is 00037 type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0); 00038 signal RAMarray : RAMarrayT:=(others => X"000000000"); 00039 signal RD_int : std_logic_vector(35 downto 0); 00040 00041 begin 00042 00043 RD_int <= RAMarray(to_integer(unsigned(RADDR))); 00044 00045 00046 process(RWclk,reset) 00047 begin 00048 if reset = '0' then 00049 RD <= (X"000000000"); 00050 rst:for i in 0 to 255 loop 00051 RAMarray(i) <= (others => '0'); 00052 end loop; 00053 00054 elsif RWclk'event and RWclk = '1' then 00055 if REN = '0' then 00056 RD <= RD_int; 00057 end if; 00058 00059 if WEN = '0' then 00060 RAMarray(to_integer(unsigned(WADDR))) <= WD; 00061 end if; 00062 00063 end if; 00064 end process; 00065 end ar_RAM_CEL; 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet