Inherits RAM_CEL::ar_RAM_CEL.
Inherited by ar_FILTER_RAM_CTRLR, iir_filter [private], and ar_RAM_CTRLR2.
Architectures | |
| ar_RAM_CEL | Architecture |
Libraries | |
| ieee | |
Packages | |
| std_logic_1164 | |
| numeric_std | |
Ports | |
| WD | in std_logic_vector ( 35 downto 0 ) |
| RD | out std_logic_vector ( 35 downto 0 ) |
| REN | in std_logic |
| WEN | in std_logic |
| WADDR | in std_logic_vector ( 7 downto 0 ) |
| RADDR | in std_logic_vector ( 7 downto 0 ) |
| RESET | in std_logic |
| RWCLK | in std_logic |
Definition at line 26 of file RAM_CEL.vhd.
ieee library [Library] |
Definition at line 22 of file RAM_CEL.vhd.
numeric_std package [Package] |
Definition at line 24 of file RAM_CEL.vhd.
RADDR in std_logic_vector ( 7 downto 0 ) [Port] |
Definition at line 29 of file RAM_CEL.vhd.
RD out std_logic_vector ( 35 downto 0 ) [Port] |
Definition at line 27 of file RAM_CEL.vhd.
REN in std_logic [Port] |
Definition at line 28 of file RAM_CEL.vhd.
RESET in std_logic [Port] |
Definition at line 30 of file RAM_CEL.vhd.
RWCLK in std_logic [Port] |
Definition at line 30 of file RAM_CEL.vhd.
std_logic_1164 package [Package] |
Definition at line 23 of file RAM_CEL.vhd.
WADDR in std_logic_vector ( 7 downto 0 ) [Port] |
Definition at line 29 of file RAM_CEL.vhd.
WD in std_logic_vector ( 35 downto 0 ) [Port] |
Definition at line 27 of file RAM_CEL.vhd.
WEN in std_logic [Port] |
Definition at line 28 of file RAM_CEL.vhd.