00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ---------------------------------------------------------------------------- 00022 library IEEE; 00023 use IEEE.numeric_std.all; 00024 use IEEE.std_logic_1164.all; 00025 library lpp; 00026 use lpp.general_purpose.all; 00027 00028 entity REG is 00029 generic(size : integer := 16 ; initial_VALUE : integer := 0); 00030 port( 00031 reset : in std_logic; 00032 clk : in std_logic; 00033 D : in std_logic_vector(size-1 downto 0); 00034 Q : out std_logic_vector(size-1 downto 0) 00035 ); 00036 end entity; 00037 00038 00039 00040 architecture ar_REG of REG is 00041 begin 00042 process(clk,reset) 00043 begin 00044 if reset = '0' then 00045 Q <= std_logic_vector(to_unsigned(initial_VALUE,size)); 00046 elsif clk'event and clk ='1' then 00047 Q <= D; 00048 end if; 00049 end process; 00050 end ar_REG;
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet