| addr_max_int | Fifo_Read | [Generic] |
| Addr_sz | Fifo_Read | [Generic] |
| clk | Fifo_Read | [Port] |
| empty | Fifo_Read | [Port] |
| flag_RE | Fifo_Read | [Port] |
| flag_reg | ar_Fifo_Read | [Signal] |
| IEEE | Fifo_Read | [Library] |
| numeric_std | Fifo_Read | [Package] |
| PROCESS_33(clk, raz) | ar_Fifo_Read | [Process] |
| Rad_int | ar_Fifo_Read | [Signal] |
| Rad_int_reg | ar_Fifo_Read | [Signal] |
| Raddr | Fifo_Read | [Port] |
| raz | Fifo_Read | [Port] |
| std_logic_1164 | Fifo_Read | [Package] |
| Wad_int | ar_Fifo_Read | [Signal] |
| Wad_int_reg | ar_Fifo_Read | [Signal] |
| Waddr | Fifo_Read | [Port] |