| ieee | RAM_CEL | [Library] |
| numeric_std | RAM_CEL | [Package] |
| PROCESS_12(RWclk, reset) | ar_RAM_CEL | [Process] |
| RADDR | RAM_CEL | [Port] |
| RAMarray | ar_RAM_CEL | [Signal] |
| RAMarrayT | ar_RAM_CEL | [Type] |
| RD | RAM_CEL | [Port] |
| RD_int | ar_RAM_CEL | [Signal] |
| REN | RAM_CEL | [Port] |
| RESET | RAM_CEL | [Port] |
| RWCLK | RAM_CEL | [Port] |
| std_logic_1164 | RAM_CEL | [Package] |
| WADDR | RAM_CEL | [Port] |
| WD | RAM_CEL | [Port] |
| WEN | RAM_CEL | [Port] |