| clk | Serialize | [Port] |
| CPT_ended | ar_Serialize | [Signal] |
| Data | Serialize | [Port] |
| ect | ar_Serialize | [Signal] |
| etat | ar_Serialize | [Type] |
| IEEE | Serialize | [Library] |
| load | ar_Serialize | [Signal] |
| N | ar_Serialize | [Signal] |
| numeric_std | Serialize | [Package] |
| PROCESS_29(clk, raz) | ar_Serialize | [Process] |
| PROCESS_30(sclk, load, raz) | ar_Serialize | [Process] |
| raz | Serialize | [Port] |
| sclk | Serialize | [Port] |
| send | Serialize | [Port] |
| sended | Serialize | [Port] |
| std_logic_1164 | Serialize | [Package] |
| vectin | Serialize | [Port] |
| vectin_reg | ar_Serialize | [Signal] |
| vector_int | ar_Serialize | [Signal] |