ar_Serialize Architecture Reference

Inherited by Serialize.

List of all members.



Processes

PROCESS_29  ( clk , raz )
PROCESS_30  ( sclk , load , raz )

Types

etat  ( attente , serialize )

Signals

ect  etat
vector_int  std_logic_vector ( 16 downto 0 )
vectin_reg  std_logic_vector ( 15 downto 0 )
load  std_logic
N  integer range 0 to 16
CPT_ended  std_logic := ' 0 '

Detailed Description

Definition at line 40 of file Serialize.vhd.


Member Function Documentation

[Process]
PROCESS_29 ( clk ,
raz )

Definition at line 52 of file Serialize.vhd.

[Process]
PROCESS_30 ( sclk ,
load ,
raz )

Definition at line 84 of file Serialize.vhd.


Member Data Documentation

CPT_ended std_logic := ' 0 ' [Signal]

Definition at line 49 of file Serialize.vhd.

ect etat [Signal]

Definition at line 43 of file Serialize.vhd.

etat ( attente , serialize ) [Type]

Definition at line 42 of file Serialize.vhd.

load std_logic [Signal]

Definition at line 47 of file Serialize.vhd.

N integer range 0 to 16 [Signal]

Definition at line 48 of file Serialize.vhd.

vectin_reg std_logic_vector ( 15 downto 0 ) [Signal]

Definition at line 46 of file Serialize.vhd.

vector_int std_logic_vector ( 16 downto 0 ) [Signal]

Definition at line 45 of file Serialize.vhd.


The documentation for this class was generated from the following file: