Programme qui va permetre de générer l'horloge systeme (sclk). More...
Inherits Systeme_Clock::ar_Systeme_Clock.
Inherited by ar_CNA_TabloC, and lpp_cna [private].
Architectures | |
| ar_Systeme_Clock | Architecture |
Libraries | |
| IEEE | |
Packages | |
| std_logic_1164 | |
| numeric_std | |
Generics | |
| N | integer := 695 |
| Générique contenant le résultat de la division clk/sclk. | |
Ports | |
| raz | in std_logic |
| Horloge et Reset globale du composant. | |
| clk | in std_logic |
| Horloge et Reset globale du composant. | |
| sclk | out std_logic |
| Horloge Systeme générée. | |
Programme qui va permetre de générer l'horloge systeme (sclk).
Definition at line 28 of file Systeme_Clock.vhd.
clk in std_logic [Port] |
Horloge et Reset globale du composant.
Definition at line 31 of file Systeme_Clock.vhd.
IEEE library [Library] |
Definition at line 22 of file Systeme_Clock.vhd.
N integer := 695 [Generic] |
Générique contenant le résultat de la division clk/sclk.
Definition at line 29 of file Systeme_Clock.vhd.
numeric_std package [Package] |
Definition at line 24 of file Systeme_Clock.vhd.
raz in std_logic [Port] |
Horloge et Reset globale du composant.
Definition at line 31 of file Systeme_Clock.vhd.
sclk out std_logic [Port] |
Horloge Systeme générée.
Definition at line 32 of file Systeme_Clock.vhd.
std_logic_1164 package [Package] |
Definition at line 23 of file Systeme_Clock.vhd.