00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ---------------------------------------------------------------------------- 00022 00023 library IEEE; 00024 use IEEE.STD_LOGIC_1164.all; 00025 library grlib; 00026 use grlib.amba.all; 00027 use grlib.stdlib.all; 00028 use grlib.devices.all; 00029 00030 00031 package lpp_ad_conv is 00032 00033 00034 constant AD7688 : integer := 0; 00035 constant ADS7886 : integer := 1; 00036 00037 00038 type AD7688_out is 00039 record 00040 CNV : std_logic; 00041 SCK : std_logic; 00042 end record; 00043 00044 type AD7688_in_element is 00045 record 00046 SDI : std_logic; 00047 end record; 00048 00049 type AD7688_in is array(natural range <>) of AD7688_in_element; 00050 00051 type Samples_out is array(natural range <>) of std_logic_vector(15 downto 0); 00052 00053 component AD7688_drvr is 00054 generic(ChanelCount : integer; 00055 clkkHz : integer); 00056 Port ( clk : in STD_LOGIC; 00057 reset : in STD_LOGIC; 00058 smplClk: in STD_LOGIC; 00059 DataReady : out std_logic; 00060 smpout : out Samples_out(ChanelCount-1 downto 0); 00061 AD_in : in AD7688_in(ChanelCount-1 downto 0); 00062 AD_out : out AD7688_out); 00063 end component; 00064 00065 00066 component AD7688_spi_if is 00067 generic(ChanelCount : integer); 00068 Port( clk : in STD_LOGIC; 00069 reset : in STD_LOGIC; 00070 cnv : in STD_LOGIC; 00071 DataReady: out std_logic; 00072 sdi : in AD7688_in(ChanelCount-1 downto 0); 00073 smpout : out Samples_out(ChanelCount-1 downto 0) 00074 ); 00075 end component; 00076 00077 00078 component lpp_apb_ad_conv 00079 generic( 00080 pindex : integer := 0; 00081 paddr : integer := 0; 00082 pmask : integer := 16#fff#; 00083 pirq : integer := 0; 00084 abits : integer := 8; 00085 ChanelCount : integer := 1; 00086 clkkHz : integer := 50000; 00087 smpClkHz : integer := 100; 00088 ADCref : integer := AD7688); 00089 Port ( 00090 clk : in STD_LOGIC; 00091 reset : in STD_LOGIC; 00092 apbi : in apb_slv_in_type; 00093 apbo : out apb_slv_out_type; 00094 AD_in : in AD7688_in(ChanelCount-1 downto 0); 00095 AD_out : out AD7688_out); 00096 end component; 00097 00098 component ADS7886_drvr is 00099 generic(ChanelCount : integer; 00100 clkkHz : integer); 00101 Port ( 00102 clk : in STD_LOGIC; 00103 reset : in STD_LOGIC; 00104 smplClk : in STD_LOGIC; 00105 DataReady : out std_logic; 00106 smpout : out Samples_out(ChanelCount-1 downto 0); 00107 AD_in : in AD7688_in(ChanelCount-1 downto 0); 00108 AD_out : out AD7688_out 00109 ); 00110 end component; 00111 00112 00113 end lpp_ad_conv; 00114 00115
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet