00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ---------------------------------------------------------------------------- 00022 library IEEE; 00023 use IEEE.STD_LOGIC_1164.ALL; 00024 library lpp; 00025 use lpp.lpp_ad_conv.all; 00026 use lpp.general_purpose.Clk_divider; 00027 00028 entity ADS7886_drvr is 00029 generic(ChanelCount : integer; 00030 clkkHz : integer); 00031 Port ( clk : in STD_LOGIC; 00032 reset : in STD_LOGIC; 00033 smplClk: in STD_LOGIC; 00034 DataReady : out std_logic; 00035 smpout : out Samples_out(ChanelCount-1 downto 0); 00036 AD_in : in AD7688_in(ChanelCount-1 downto 0); 00037 AD_out : out AD7688_out); 00038 end ADS7886_drvr; 00039 00040 architecture ar_ADS7886_drvr of ADS7886_drvr is 00041 00042 constant convTrigger : integer:= clkkHz*1/1000; --tconv = 1.6µs 00043 00044 signal i : integer range 0 to convTrigger :=0; 00045 signal clk_int : std_logic; 00046 signal smplClk_reg : std_logic; 00047 signal cnv_int : std_logic; 00048 signal smpout_int : Samples_out(ChanelCount-1 downto 0); 00049 00050 00051 begin 00052 00053 00054 clkdiv: if clkkHz>=20000 generate 00055 clkdivider: Clk_divider 00056 generic map(clkkHz*1000,19000000) 00057 Port map( clk ,reset,clk_int); 00058 end generate; 00059 00060 00061 clknodiv: if clkkHz<20000 generate 00062 nodiv: clk_int <= clk; 00063 end generate; 00064 00065 AD_out.CNV <= cnv_int; 00066 AD_out.SCK <= clk_int; 00067 00068 00069 sckgen: process(clk,reset) 00070 begin 00071 if reset = '0' then 00072 i <= 0; 00073 cnv_int <= '0'; 00074 smplClk_reg <= '0'; 00075 elsif clk'event and clk = '1' then 00076 if smplClk = '1' and smplClk_reg = '0' then 00077 if i = convTrigger then 00078 smplClk_reg <= '1'; 00079 i <= 0; 00080 cnv_int <= '0'; 00081 else 00082 i <= i+1; 00083 cnv_int <= '1'; 00084 end if; 00085 elsif smplClk = '0' and smplClk_reg = '1' then 00086 smplClk_reg <= '0'; 00087 end if; 00088 end if; 00089 end process; 00090 00091 00092 NDMSK: for i in 0 to ChanelCount-1 00093 generate 00094 smpout(i) <= smpout_int(i) and X"0FFF"; 00095 end generate; 00096 00097 00098 spidrvr: AD7688_spi_if 00099 generic map(ChanelCount) 00100 Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout_int); 00101 00102 00103 00104 end ar_ADS7886_drvr; 00105
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet