Inherits Clk_divider::ar_Clk_divider.
Inherited by ar_AD7688_drvr, ar_ADS7886_drvr, general_purpose [private], and ar_lpp_apb_ad_conv.
Architectures | |
| ar_Clk_divider | Architecture |
Libraries | |
| IEEE | |
Packages | |
| STD_LOGIC_1164 | |
Generics | |
| OSC_freqHz | integer := 50000000 |
| TargetFreq_Hz | integer := 50000 |
Ports | |
| clk | in std_logic |
| reset | in std_logic |
| clk_divided | out std_logic |
Definition at line 26 of file Clk_divider.vhd.
clk in std_logic [Port] |
Reimplemented in lpp_apb_ad_conv.
Definition at line 29 of file Clk_divider.vhd.
clk_divided out std_logic [Port] |
Definition at line 31 of file Clk_divider.vhd.
IEEE library [Library] |
Reimplemented in lpp_apb_ad_conv.
Definition at line 22 of file Clk_divider.vhd.
OSC_freqHz integer := 50000000 [Generic] |
Definition at line 27 of file Clk_divider.vhd.
reset in std_logic [Port] |
Reimplemented in lpp_apb_ad_conv.
Definition at line 30 of file Clk_divider.vhd.
STD_LOGIC_1164 package [Package] |
Reimplemented in lpp_apb_ad_conv.
Definition at line 23 of file Clk_divider.vhd.
TargetFreq_Hz integer := 50000 [Generic] |
Definition at line 28 of file Clk_divider.vhd.