00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ---------------------------------------------------------------------------- 00022 library IEEE; 00023 use IEEE.numeric_std.all; 00024 use IEEE.std_logic_1164.all; 00025 library lpp; 00026 use lpp.general_purpose.all; 00027 --IDLE =0000 MAC =0001 MULT =0010 ADD =0011 CLRMAC =0100 00028 --NOT =0101 AND =0110 OR =0111 XOR =1000 00029 --SHIFTleft =1001 SHIFTright =1010 00030 00031 entity ALU is 00032 generic( 00033 Arith_en : integer := 1; 00034 Logic_en : integer := 1; 00035 Input_SZ_1 : integer := 16; 00036 Input_SZ_2 : integer := 9 00037 00038 ); 00039 port( 00040 clk : in std_logic; 00041 reset : in std_logic; 00042 ctrl : in std_logic_vector(3 downto 0); 00043 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); 00044 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); 00045 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) 00046 ); 00047 end entity; 00048 00049 00050 00051 architecture ar_ALU of ALU is 00052 00053 00054 00055 signal clr_MAC : std_logic:='1'; 00056 00057 00058 begin 00059 00060 clr_MAC <= '1' when ctrl = "0100" else '0'; 00061 00062 00063 arith : if Arith_en = 1 generate 00064 MACinst : MAC 00065 generic map(Input_SZ_1,Input_SZ_2) 00066 port map(clk,reset,clr_MAC,ctrl(1 downto 0),OP1,OP2,RES); 00067 end generate; 00068 00069 end architecture; 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet