Inherits MAC::ar_MAC.
Inherited by ar_ALU, general_purpose [private], and ar_TestbenshMAC.
Architectures | |
| ar_MAC | Architecture |
Libraries | |
| IEEE | |
| lpp | |
Packages | |
| numeric_std | |
| std_logic_1164 | |
| general_purpose | Package <general_purpose> |
Generics | |
| Input_SZ_A | integer := 8 |
| Input_SZ_B | integer := 8 |
Ports | |
| clk | in std_logic |
| reset | in std_logic |
| clr_MAC | in std_logic |
| MAC_MUL_ADD | in std_logic_vector ( 1 downto 0 ) |
| OP1 | in std_logic_vector ( Input_SZ_A -1 downto 0 ) |
| OP2 | in std_logic_vector ( Input_SZ_B -1 downto 0 ) |
| RES | out std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 ) |
Definition at line 35 of file MAC.vhd.
clk in std_logic [Port] |
Reimplemented in APB_IIR_CEL, IIR_CEL_CTRLR, IIR_CEL_FILTER, ar_TestbenshMAC, ALU, and ar_TestbenshALU.
general_purpose package [Package] |
Reimplemented from MAC_MUX2.
Reimplemented in APB_IIR_CEL, IIR_CEL_CTRLR, IIR_CEL_FILTER, and ALU.
IEEE library [Library] |
Reimplemented from MAC_MUX2.
Reimplemented in IIR_CEL_CTRLR, IIR_CEL_FILTER, TestbenshMAC, ALU, and TestbenshALU.
Input_SZ_A integer := 8 [Generic] |
Input_SZ_B integer := 8 [Generic] |
lpp library [Library] |
Reimplemented from MAC_MUX2.
Reimplemented in APB_IIR_CEL, IIR_CEL_CTRLR, IIR_CEL_FILTER, and ALU.
MAC_MUL_ADD in std_logic_vector ( 1 downto 0 ) [Port] |
Reimplemented in ar_TestbenshMAC.
numeric_std package [Package] |
Reimplemented from MAC_MUX2.
Reimplemented in APB_IIR_CEL, IIR_CEL_CTRLR, IIR_CEL_FILTER, TestbenshMAC, ALU, and TestbenshALU.
OP1 in std_logic_vector ( Input_SZ_A -1 downto 0 ) [Port] |
OP2 in std_logic_vector ( Input_SZ_B -1 downto 0 ) [Port] |
RES out std_logic_vector ( Input_SZ_A +Input_SZ_B -1 downto 0 ) [Port] |
reset in std_logic [Port] |
Reimplemented in IIR_CEL_CTRLR, IIR_CEL_FILTER, ar_TestbenshMAC, ALU, and ar_TestbenshALU.
std_logic_1164 package [Package] |
Reimplemented from MAC_MUX2.
Reimplemented in APB_IIR_CEL, IIR_CEL_CTRLR, IIR_CEL_FILTER, TestbenshMAC, ALU, and TestbenshALU.