00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ---------------------------------------------------------------------------- 00022 library IEEE; 00023 use IEEE.numeric_std.all; 00024 use IEEE.std_logic_1164.all; 00025 library lpp; 00026 use lpp.general_purpose.all; 00027 00028 00029 00030 entity Adder is 00031 generic( 00032 Input_SZ_A : integer := 16; 00033 Input_SZ_B : integer := 16 00034 00035 ); 00036 port( 00037 clk : in std_logic; 00038 reset : in std_logic; 00039 clr : in std_logic; 00040 add : in std_logic; 00041 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); 00042 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); 00043 RES : out std_logic_vector(Input_SZ_A-1 downto 0) 00044 ); 00045 end entity; 00046 00047 00048 00049 00050 architecture ar_Adder of Adder is 00051 00052 signal REG : std_logic_vector(Input_SZ_A-1 downto 0); 00053 signal RESADD : std_logic_vector(Input_SZ_A-1 downto 0); 00054 00055 begin 00056 00057 RES <= REG; 00058 RESADD <= std_logic_vector(resize(signed(OP1)+signed(OP2),Input_SZ_A)); 00059 00060 process(clk,reset) 00061 begin 00062 if reset = '0' then 00063 REG <= (others => '0'); 00064 elsif clk'event and clk ='1' then 00065 if clr = '1' then 00066 REG <= (others => '0'); 00067 elsif add = '1' then 00068 REG <= RESADD; 00069 end if; 00070 end if; 00071 end process; 00072 end ar_Adder;
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet