ar_Adder Architecture Reference

Inherited by Adder.

List of all members.

Processes
PROCESS_15	( clk , reset )
Signals
REG	std_logic_vector ( Input_SZ_A -1 downto 0 )
RESADD	std_logic_vector ( Input_SZ_A -1 downto 0 )

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Detailed Description

Definition at line 50 of file Adder.vhd.

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Member Function Documentation

[Process]

PROCESS_15		( clk ,
		reset )

Definition at line 60 of file Adder.vhd.

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Member Data Documentation

REG std_logic_vector ( Input_SZ_A -1 downto 0 ) [Signal]

Definition at line 52 of file Adder.vhd.

RESADD std_logic_vector ( Input_SZ_A -1 downto 0 ) [Signal]

Definition at line 53 of file Adder.vhd.

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The documentation for this class was generated from the following file:

• general_purpose/Adder.vhd