00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ---------------------------------------------------------------------------- 00022 library IEEE; 00023 use IEEE.numeric_std.all; 00024 use IEEE.std_logic_1164.all; 00025 00027 00029 00030 entity BaudGen is 00031 00032 port( 00033 clk : in std_logic; 00034 reset : in std_logic; 00035 Capture : in std_logic; 00036 Bclk : out std_logic; 00037 RXD : in std_logic; 00038 BTrigger : out std_logic_vector(11 downto 0) 00039 ); 00040 end BaudGen; 00041 00042 00043 architecture ar_BaudGen of BaudGen is 00044 signal cpt : std_logic_vector(11 downto 0) := (others => '0'); 00045 signal errorFlag : std_logic; 00046 signal triger : std_logic_vector(11 downto 0) := (others => '0'); 00047 signal RX_reg : std_logic:='1'; 00048 00049 begin 00050 00051 00052 BTrigger <= triger; 00053 00054 00055 BaudGeneration: 00056 process(clk,reset) 00057 begin 00058 if reset = '0' then 00059 cpt <= (others => '0'); 00060 triger <= (others => '1'); 00061 errorFlag <= '0'; 00062 elsif clk'event and clk = '1'then 00063 RX_reg <= RXD; 00064 if capture = '1' then 00065 cpt <= (others => '0'); 00066 triger <= (others => '1'); 00067 errorFlag <= '0'; 00068 else 00069 if RX_reg /= RXD then 00070 cpt <= (others => '0'); 00071 if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then 00072 errorFlag <= '1'; 00073 elsif errorFlag = '1' then 00074 triger <= cpt; 00075 errorFlag <= '0'; 00076 else 00077 errorFlag <= '1'; 00078 end if; 00079 else 00080 if cpt = triger then 00081 cpt <= (others => '0'); 00082 errorFlag <= '0'; 00083 else 00084 cpt <= std_logic_vector(unsigned(cpt) + 1); 00085 end if; 00086 end if; 00087 end if; 00088 end if; 00089 end process; 00090 00091 00092 process(clk) 00093 begin 00094 if clk'event and clk = '1' then 00095 if cpt = std_logic_vector(TO_UNSIGNED(0,12)) then 00096 Bclk <= '0'; 00097 elsif cpt = '0' & triger(11 downto 1) then 00098 Bclk <= '1'; 00099 end if; 00100 end if; 00101 end process; 00102 00103 00104 end ar_BaudGen;
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet