BaudGen Entity Reference

This is an automatic Baud generator. To synchronize baudrate, it measure the smalest time between two transitions of RXD. So to set baud rate, the device connected to this UART should send at least one data such as 0xA5 (0b10100101) witch gives a lot of transition of one bit length. More...

Inherits BaudGen::ar_BaudGen.

Inherited by lpp_uart [private], and ar_UART.

List of all members.



Architectures

ar_BaudGen Architecture

Libraries

IEEE 

Packages

numeric_std 
std_logic_1164 

Ports

clk  in std_logic
 System clock.
reset  in std_logic
 System reset.
Capture  in std_logic
 baudrate reset so if you want to synchronize again the baudrate generator, usefull if you whant to decrease speed.
Bclk  out std_logic
 Output baud clock.
RXD  in std_logic
 UART Reception pin used to sample baudrate.
BTrigger  out std_logic_vector ( 11 downto 0 )
 Current value of the frequency divider.

Detailed Description

This is an automatic Baud generator. To synchronize baudrate, it measure the smalest time between two transitions of RXD. So to set baud rate, the device connected to this UART should send at least one data such as 0xA5 (0b10100101) witch gives a lot of transition of one bit length.

Author:
Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr

Definition at line 30 of file BaudGen.vhd.


Member Data Documentation

Bclk out std_logic [Port]

Output baud clock.

Definition at line 36 of file BaudGen.vhd.

BTrigger out std_logic_vector ( 11 downto 0 ) [Port]

Current value of the frequency divider.

Definition at line 38 of file BaudGen.vhd.

Capture in std_logic [Port]

baudrate reset so if you want to synchronize again the baudrate generator, usefull if you whant to decrease speed.

Definition at line 35 of file BaudGen.vhd.

clk in std_logic [Port]

System clock.

Definition at line 33 of file BaudGen.vhd.

IEEE library [Library]

Definition at line 22 of file BaudGen.vhd.

numeric_std package [Package]

Definition at line 23 of file BaudGen.vhd.

reset in std_logic [Port]

System reset.

Definition at line 34 of file BaudGen.vhd.

RXD in std_logic [Port]

UART Reception pin used to sample baudrate.

Definition at line 37 of file BaudGen.vhd.

std_logic_1164 package [Package]

Definition at line 24 of file BaudGen.vhd.


The documentation for this class was generated from the following file: