00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------ 00019 -- Author : Martin Morlot 00020 -- Mail : martin.morlot@lpp.polytechnique.fr 00021 ------------------------------------------------------------------------------ 00022 library IEEE; 00023 use IEEE.std_logic_1164.all; 00024 use IEEE.numeric_std.all; 00025 00027 00028 entity Fifo_Write is 00029 generic( 00030 Addr_sz : integer := 8; 00031 addr_max_int : integer := 256); 00032 port( 00033 clk,raz : in std_logic; 00034 flag_WR : in std_logic; 00035 Raddr : in std_logic_vector(addr_sz-1 downto 0); 00036 full : out std_logic; 00037 Waddr : out std_logic_vector(addr_sz-1 downto 0) 00038 ); 00039 end Fifo_Write; 00040 00042 00043 architecture ar_Fifo_Write of Fifo_Write is 00044 00045 signal Wad_int : integer range 0 to addr_max_int; 00046 signal Wad_int_reg : integer range 0 to addr_max_int; 00047 signal Rad_int : integer range 0 to addr_max_int; 00048 signal Rad_int_reg : integer range 0 to addr_max_int; 00049 00050 begin 00051 process (clk,raz) 00052 begin 00053 if(raz='0')then 00054 Wad_int <= 0; 00055 full <= '0'; 00056 00057 elsif(clk' event and clk='1')then 00058 Wad_int_reg <= Wad_int; 00059 Rad_int_reg <= Rad_int; 00060 00061 00062 if(flag_WR='1')then 00063 if(Wad_int=addr_max_int-1)then 00064 Wad_int <= 0; 00065 else 00066 Wad_int <= Wad_int+1; 00067 end if; 00068 end if; 00069 00070 if(Wad_int_reg /= Wad_int)then 00071 if(Wad_int=Rad_int)then 00072 full <= '1'; 00073 else 00074 full <= '0'; 00075 end if; 00076 elsif(Rad_int_reg /= Rad_int)then 00077 full <= '0'; 00078 end if; 00079 00080 end if; 00081 end process; 00082 00083 Rad_int <= to_integer(unsigned(Raddr)); 00084 Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz)); 00085 00086 end ar_Fifo_Write;
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet