Inherited by Fifo_Write.
Processes | |
| PROCESS_34 | ( clk , raz ) |
Signals | |
| Wad_int | integer range 0 to addr_max_int |
| Wad_int_reg | integer range 0 to addr_max_int |
| Rad_int | integer range 0 to addr_max_int |
| Rad_int_reg | integer range 0 to addr_max_int |
En amont de la SRAM Gaisler
Definition at line 43 of file Fifo_Write.vhd.
| PROCESS_34 | ( clk , | |
| raz ) |
Definition at line 51 of file Fifo_Write.vhd.
Rad_int integer range 0 to addr_max_int [Signal] |
Definition at line 47 of file Fifo_Write.vhd.
Rad_int_reg integer range 0 to addr_max_int [Signal] |
Definition at line 48 of file Fifo_Write.vhd.
Wad_int integer range 0 to addr_max_int [Signal] |
Definition at line 45 of file Fifo_Write.vhd.
Wad_int_reg integer range 0 to addr_max_int [Signal] |
Definition at line 46 of file Fifo_Write.vhd.