Fifo_Write Entity Reference

Programme de la FIFO d'écriture. More...

Inherits Fifo_Write::ar_Fifo_Write.

Inherited by lpp_memory [private], ar_Top_FIFO, and ar_Top_FifoWrite.

List of all members.



Architectures

ar_Fifo_Write Architecture

Libraries

IEEE 

Packages

std_logic_1164 
numeric_std 

Generics

Addr_sz  integer := 8
addr_max_int  integer := 256

Ports

raz  in std_logic
 Horloge et reset general du composant.
clk  in std_logic
 Horloge et reset general du composant.
flag_WR  in std_logic
 Flag, Demande l'écriture dans la mémoire.
Raddr  in std_logic_vector ( Addr_sz -1 downto 0 )
 Adresse du registre de lecture de la mémoire.
full  out std_logic
 Flag, Mémoire pleine.
Waddr  out std_logic_vector ( Addr_sz -1 downto 0 )
 Adresse du registre d'écriture dans la mémoire.

Detailed Description

Programme de la FIFO d'écriture.

Definition at line 28 of file Fifo_Write.vhd.


Member Data Documentation

addr_max_int integer := 256 [Generic]

Reimplemented in APB_FifoWrite, and Top_FifoWrite.

Definition at line 31 of file Fifo_Write.vhd.

Addr_sz integer := 8 [Generic]

Reimplemented in APB_FifoWrite, and Top_FifoWrite.

Definition at line 30 of file Fifo_Write.vhd.

clk in std_logic [Port]

Horloge et reset general du composant.

Reimplemented in APB_FifoWrite, and Top_FifoWrite.

Definition at line 33 of file Fifo_Write.vhd.

flag_WR in std_logic [Port]

Flag, Demande l'écriture dans la mémoire.

Reimplemented in Top_FifoWrite.

Definition at line 34 of file Fifo_Write.vhd.

full out std_logic [Port]

Flag, Mémoire pleine.

Reimplemented in Top_FifoWrite.

Definition at line 36 of file Fifo_Write.vhd.

IEEE library [Library]

Reimplemented in Top_FifoWrite.

Definition at line 22 of file Fifo_Write.vhd.

numeric_std package [Package]

Reimplemented in Top_FifoWrite.

Definition at line 24 of file Fifo_Write.vhd.

Raddr in std_logic_vector ( Addr_sz -1 downto 0 ) [Port]

Adresse du registre de lecture de la mémoire.

Reimplemented in APB_FifoWrite, and Top_FifoWrite.

Definition at line 35 of file Fifo_Write.vhd.

raz in std_logic [Port]

Horloge et reset general du composant.

Reimplemented in Top_FifoWrite.

Definition at line 33 of file Fifo_Write.vhd.

std_logic_1164 package [Package]

Reimplemented in APB_FifoWrite, and Top_FifoWrite.

Definition at line 23 of file Fifo_Write.vhd.

Waddr out std_logic_vector ( Addr_sz -1 downto 0 ) [Port]

Adresse du registre d'écriture dans la mémoire.

Reimplemented in Top_FifoWrite.

Definition at line 37 of file Fifo_Write.vhd.


The documentation for this class was generated from the following file: