00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ---------------------------------------------------------------------------- 00022 library IEEE; 00023 use IEEE.numeric_std.all; 00024 use IEEE.std_logic_1164.all; 00025 00026 library lpp; 00027 use lpp.general_purpose.all; 00028 00029 00030 00031 entity Multiplier is 00032 generic( 00033 Input_SZ_A : integer := 16; 00034 Input_SZ_B : integer := 16 00035 00036 ); 00037 port( 00038 clk : in std_logic; 00039 reset : in std_logic; 00040 mult : in std_logic; 00041 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); 00042 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); 00043 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) 00044 ); 00045 end Multiplier; 00046 00047 00048 00049 00050 00051 architecture ar_Multiplier of Multiplier is 00052 00053 signal REG : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); 00054 signal RESMULT : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0); 00055 00056 00057 begin 00058 00059 RES <= REG; 00060 RESMULT <= std_logic_vector(signed(OP1)*signed(OP2)); 00061 process(clk,reset) 00062 begin 00063 if reset = '0' then 00064 REG <= (others => '0'); 00065 elsif clk'event and clk ='1' then 00066 if mult = '1' then 00067 REG <= RESMULT; 00068 end if; 00069 end if; 00070 end process; 00071 00072 end ar_Multiplier; 00073 00074 00075 00076 00077 00078 00079 00080
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet