00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ---------------------------------------------------------------------------- 00022 library IEEE; 00023 use IEEE.numeric_std.all; 00024 use IEEE.std_logic_1164.all; 00025 00030 00031 entity Shift_REG is 00032 generic( 00033 Data_sz : integer := 10 00034 ); 00035 port( 00036 clk : in std_logic; 00037 Sclk : in std_logic; 00038 reset : in std_logic; 00039 SIN : in std_logic; 00040 SOUT : out std_logic; 00041 Serialize : in std_logic; 00042 Serialized : out std_logic; 00043 D : in std_logic_vector(Data_sz-1 downto 0); 00044 Q : out std_logic_vector(Data_sz-1 downto 0) 00045 ); 00046 end entity; 00047 00048 00049 architecture ar_Shift_REG of Shift_REG is 00050 00051 signal REG : std_logic_vector(Data_sz-1 downto 0); 00052 signal Serialized_int : std_logic; 00053 signal Serialize_reg : std_logic; 00054 signal Serial_reg : std_logic; 00055 signal CptBits : std_logic_vector(Data_sz-1 downto 0); 00056 constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1'); 00057 signal CptBits_flag : std_logic; 00058 signal CptBits_flag_reg : std_logic; 00059 00060 begin 00061 00062 Serialized <= Serialized_int; 00063 CptBits_flag <= '1' when CptBits = CptBits_trig else '0'; 00064 00065 process(reset,clk) 00066 begin 00067 if reset = '0' then 00068 Serialized_int <= '1'; 00069 CptBits_flag_reg <= '0'; 00070 Serial_reg <= '0'; 00071 Q <= (others => '0'); 00072 elsif clk'event and clk = '1' then 00073 CptBits_flag_reg <= CptBits_flag; 00074 Serial_reg <= Serialize; 00075 00076 if CptBits_flag = '1' and CptBits_flag_reg = '0' then 00077 Serialized_int <= '1'; 00078 Q <= REG; 00079 elsif(Serial_reg='0' and Serialize='1')then 00080 Serialized_int <= '0'; 00081 end if; 00082 end if; 00083 end process; 00084 00085 00086 process(reset,Sclk) 00087 begin 00088 if reset = '0' then 00089 CptBits <= (others => '0'); 00090 REG <= (others => '0'); 00091 SOUT <= '1'; 00092 Serialize_reg <= '0'; 00093 elsif Sclk'event and Sclk = '1' then 00094 Serialize_reg <= Serialized_int; 00095 if (Serialized_int = '0' and Serialize_reg ='1') then 00096 REG <= SIN & D(Data_sz-1 downto 1); 00097 SOUT <= D(0); 00098 elsif Serialized_int = '0' then 00099 REG <= SIN & REG(Data_sz-1 downto 1); 00100 SOUT <= REG(0); 00101 else 00102 SOUT <= '1'; 00103 end if; 00104 if Serialized_int = '0' then 00105 if CptBits_flag = '1' then 00106 CptBits <= (others => '0'); 00107 else 00108 CptBits <= '1' & CptBits(Data_sz-1 downto 1); 00109 end if; 00110 else 00111 CptBits <= (others => '0'); 00112 end if; 00113 00114 end if; 00115 end process; 00116 00117 end ar_Shift_REG;
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet