Shift_REG Entity Reference

Universal shift register can be used to serialize or deserialize data. More...

Inherits Shift_REG::ar_Shift_REG.

Inherited by lpp_uart [private], and ar_UART.

List of all members.

Architectures
ar_Shift_REG	Architecture
Libraries
IEEE
Packages
numeric_std
std_logic_1164
Generics
Data_sz	integer := 10
	Width of the shift register.
Ports
clk	in std_logic
	System clock.
Sclk	in std_logic
	Serial clock.
reset	in std_logic
	System reset.
SIN	in std_logic
	Serial data in.
SOUT	out std_logic
	Serial data out.
Serialize	in std_logic
	Launch serialization.
Serialized	out std_logic
	Serialization complete.
D	in std_logic_vector ( Data_sz -1 downto 0 )
	Parallel data to be shifted out.
Q	out std_logic_vector ( Data_sz -1 downto 0 )
	Unserialized data.

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Detailed Description

Universal shift register can be used to serialize or deserialize data.

Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr

Todo:

move to general purpose library, explain more in detail the code and add some schematic in doc.

Definition at line 31 of file Shift_REG.vhd.

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Member Data Documentation

clk in std_logic [Port]

System clock.

Reimplemented in APB_UART, and UART.

Definition at line 36 of file Shift_REG.vhd.

D in std_logic_vector ( Data_sz -1 downto 0 ) [Port]

Parallel data to be shifted out.

Definition at line 43 of file Shift_REG.vhd.

Data_sz integer := 10 [Generic]

Width of the shift register.

Reimplemented in APB_UART, and UART.

Definition at line 33 of file Shift_REG.vhd.

IEEE library [Library]

Reimplemented in UART.

Definition at line 22 of file Shift_REG.vhd.

numeric_std package [Package]

Reimplemented in UART.

Definition at line 23 of file Shift_REG.vhd.

Q out std_logic_vector ( Data_sz -1 downto 0 ) [Port]

Unserialized data.

Definition at line 44 of file Shift_REG.vhd.

reset in std_logic [Port]

System reset.

Reimplemented in UART.

Definition at line 38 of file Shift_REG.vhd.

Sclk in std_logic [Port]

Serial clock.

Definition at line 37 of file Shift_REG.vhd.

Serialize in std_logic [Port]

Launch serialization.

Definition at line 41 of file Shift_REG.vhd.

Serialized out std_logic [Port]

Serialization complete.

Definition at line 42 of file Shift_REG.vhd.

SIN in std_logic [Port]

Serial data in.

Definition at line 39 of file Shift_REG.vhd.

SOUT out std_logic [Port]

Serial data out.

Definition at line 40 of file Shift_REG.vhd.

std_logic_1164 package [Package]

Reimplemented in APB_UART, lpp_uart, and UART.

Definition at line 24 of file Shift_REG.vhd.

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The documentation for this class was generated from the following file:

• lpp_uart/Shift_REG.vhd