ar_Shift_REG Architecture Reference

Inherited by Shift_REG.

List of all members.



Processes

PROCESS_41  ( reset , clk )
PROCESS_42  ( reset , Sclk )

Constants

CptBits_trig  std_logic_vector ( Data_sz -1 downto 0 ) := ( others = > ' 1 ' )

Signals

REG  std_logic_vector ( Data_sz -1 downto 0 )
Serialized_int  std_logic
Serialize_reg  std_logic
Serial_reg  std_logic
CptBits  std_logic_vector ( Data_sz -1 downto 0 )
CptBits_flag  std_logic
CptBits_flag_reg  std_logic

Detailed Description

Definition at line 49 of file Shift_REG.vhd.


Member Function Documentation

[Process]
PROCESS_41 ( reset ,
clk )

Definition at line 65 of file Shift_REG.vhd.

[Process]
PROCESS_42 ( reset ,
Sclk )

Definition at line 86 of file Shift_REG.vhd.


Member Data Documentation

CptBits std_logic_vector ( Data_sz -1 downto 0 ) [Signal]

Definition at line 55 of file Shift_REG.vhd.

CptBits_flag std_logic [Signal]

Definition at line 57 of file Shift_REG.vhd.

CptBits_flag_reg std_logic [Signal]

Definition at line 58 of file Shift_REG.vhd.

CptBits_trig std_logic_vector ( Data_sz -1 downto 0 ) := ( others = > ' 1 ' ) [Constant]

Definition at line 56 of file Shift_REG.vhd.

REG std_logic_vector ( Data_sz -1 downto 0 ) [Signal]

Definition at line 51 of file Shift_REG.vhd.

Serial_reg std_logic [Signal]

Definition at line 54 of file Shift_REG.vhd.

Serialize_reg std_logic [Signal]

Definition at line 53 of file Shift_REG.vhd.

Serialized_int std_logic [Signal]

Definition at line 52 of file Shift_REG.vhd.


The documentation for this class was generated from the following file: