00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ---------------------------------------------------------------------------- 00022 library IEEE; 00023 use IEEE.numeric_std.all; 00024 use IEEE.std_logic_1164.all; 00025 00026 00027 00028 entity TestbenshALU is 00029 end TestbenshALU; 00030 00031 00032 00033 00034 architecture ar_TestbenshALU of TestbenshALU is 00035 00036 00037 00038 constant OP1sz : integer := 16; 00039 constant OP2sz : integer := 12; 00040 --IDLE =00 MAC =01 MULT =10 ADD =11 00041 constant IDLE : std_logic_vector(3 downto 0) := "0000"; 00042 constant MAC : std_logic_vector(3 downto 0) := "0001"; 00043 constant MULT : std_logic_vector(3 downto 0) := "0010"; 00044 constant ADD : std_logic_vector(3 downto 0) := "0011"; 00045 constant clr_mac : std_logic_vector(3 downto 0) := "0100"; 00046 00047 signal clk : std_logic:='0'; 00048 signal reset : std_logic:='0'; 00049 signal ctrl : std_logic_vector(3 downto 0):=IDLE; 00050 signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0'); 00051 signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0'); 00052 signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0); 00053 00054 00055 00056 00057 begin 00058 00059 ALU1 : entity LPP_IIR_FILTER.ALU 00060 generic map( 00061 Arith_en => 1, 00062 Logic_en => 0, 00063 Input_SZ_1 => OP1sz , 00064 Input_SZ_2 => OP2sz 00065 00066 ) 00067 port map( 00068 clk => clk, 00069 reset => reset , 00070 ctrl => ctrl, 00071 OP1 => Operand1 , 00072 OP2 => Operand2 , 00073 RES => Resultat 00074 ); 00075 00076 00077 00078 00079 clk <= not clk after 25 ns; 00080 00081 process 00082 begin 00083 wait for 40 ns; 00084 reset <= '1'; 00085 wait for 11 ns; 00086 Operand1 <= X"0001"; 00087 Operand2 <= X"001"; 00088 ctrl <= ADD; 00089 wait for 50 ns; 00090 Operand1 <= X"0001"; 00091 Operand2 <= X"100"; 00092 wait for 50 ns; 00093 Operand1 <= X"0001"; 00094 Operand2 <= X"001"; 00095 ctrl <= MULT; 00096 wait for 50 ns; 00097 Operand1 <= X"0002"; 00098 Operand2 <= X"002"; 00099 wait for 50 ns; 00100 ctrl <= clr_mac; 00101 wait for 50 ns; 00102 Operand1 <= X"0001"; 00103 Operand2 <= X"003"; 00104 ctrl <= MAC; 00105 wait for 50 ns; 00106 Operand1 <= X"0001"; 00107 Operand2 <= X"001"; 00108 wait for 50 ns; 00109 Operand1 <= X"0011"; 00110 Operand2 <= X"003"; 00111 wait for 50 ns; 00112 Operand1 <= X"1001"; 00113 Operand2 <= X"003"; 00114 wait for 50 ns; 00115 Operand1 <= X"0001"; 00116 Operand2 <= X"000"; 00117 wait for 50 ns; 00118 Operand1 <= X"0001"; 00119 Operand2 <= X"003"; 00120 wait for 50 ns; 00121 Operand1 <= X"0101"; 00122 Operand2 <= X"053"; 00123 wait for 50 ns; 00124 ctrl <= clr_mac; 00125 wait; 00126 end process; 00127 end ar_TestbenshALU; 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet