Public Member Functions | Public Attributes

ar_TestbenshALU Architecture Reference

Inherits ALU.

Inherited by TestbenshALU.

List of all members.



Processes

PROCESS_22  ( )

Constants

OP1sz  integer := 16
OP2sz  integer := 12
IDLE  std_logic_vector ( 3 downto 0 ) := " 0000 "
MAC  std_logic_vector ( 3 downto 0 ) := " 0001 "
MULT  std_logic_vector ( 3 downto 0 ) := " 0010 "
ADD  std_logic_vector ( 3 downto 0 ) := " 0011 "
clr_mac  std_logic_vector ( 3 downto 0 ) := " 0100 "

Signals

clk  std_logic := ' 0 '
reset  std_logic := ' 0 '
ctrl  std_logic_vector ( 3 downto 0 ) := IDLE
Operand1  std_logic_vector ( OP1sz -1 downto 0 ) := ( others = > ' 0 ' )
Operand2  std_logic_vector ( OP2sz -1 downto 0 ) := ( others = > ' 0 ' )
Resultat  std_logic_vector ( OP1sz +OP2sz -1 downto 0 )

Component Instantiations

ALU1 ALU <Entity ALU>

Detailed Description

Definition at line 34 of file TestbenshALU.vhd.

Member Function Documentation

PROCESS_22 ( ) [Process]

Definition at line 82 of file TestbenshALU.vhd.

Member Data Documentation

ADD std_logic_vector ( 3 downto 0 ) := " 0011 " [Constant]

Definition at line 44 of file TestbenshALU.vhd.

ALU1 ALU [Component Instantiation]

Definition at line 59 of file TestbenshALU.vhd.

clk std_logic := ' 0 ' [Signal]

Reimplemented from ALU.

Definition at line 47 of file TestbenshALU.vhd.

clr_mac std_logic_vector ( 3 downto 0 ) := " 0100 " [Constant]

Definition at line 45 of file TestbenshALU.vhd.

ctrl std_logic_vector ( 3 downto 0 ) := IDLE [Signal]

Reimplemented from ALU.

Definition at line 49 of file TestbenshALU.vhd.

IDLE std_logic_vector ( 3 downto 0 ) := " 0000 " [Constant]

Definition at line 41 of file TestbenshALU.vhd.

MAC std_logic_vector ( 3 downto 0 ) := " 0001 " [Constant]

Definition at line 42 of file TestbenshALU.vhd.

MULT std_logic_vector ( 3 downto 0 ) := " 0010 " [Constant]

Definition at line 43 of file TestbenshALU.vhd.

OP1sz integer := 16 [Constant]

Definition at line 38 of file TestbenshALU.vhd.

OP2sz integer := 12 [Constant]

Definition at line 39 of file TestbenshALU.vhd.

Operand1 std_logic_vector ( OP1sz -1 downto 0 ) := ( others = > ' 0 ' ) [Signal]

Definition at line 50 of file TestbenshALU.vhd.

Operand2 std_logic_vector ( OP2sz -1 downto 0 ) := ( others = > ' 0 ' ) [Signal]

Definition at line 51 of file TestbenshALU.vhd.

reset std_logic := ' 0 ' [Signal]

Reimplemented from ALU.

Definition at line 48 of file TestbenshALU.vhd.

Resultat std_logic_vector ( OP1sz +OP2sz -1 downto 0 ) [Signal]

Definition at line 52 of file TestbenshALU.vhd.

The documentation for this class was generated from the following file: