00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ---------------------------------------------------------------------------- 00022 library IEEE; 00023 use IEEE.numeric_std.all; 00024 use IEEE.std_logic_1164.all; 00025 00026 00027 00028 entity TestbenshMAC is 00029 end TestbenshMAC; 00030 00031 00032 00033 00034 architecture ar_TestbenshMAC of TestbenshMAC is 00035 00036 00037 00038 constant OP1sz : integer := 16; 00039 constant OP2sz : integer := 12; 00040 --IDLE =00 MAC =01 MULT =10 ADD =11 00041 constant IDLE : std_logic_vector(1 downto 0) := "00"; 00042 constant MAC : std_logic_vector(1 downto 0) := "01"; 00043 constant MULT : std_logic_vector(1 downto 0) := "10"; 00044 constant ADD : std_logic_vector(1 downto 0) := "11"; 00045 00046 signal clk : std_logic:='0'; 00047 signal reset : std_logic:='0'; 00048 signal clrMAC : std_logic:='0'; 00049 signal MAC_MUL_ADD : std_logic_vector(1 downto 0):=IDLE; 00050 signal Operand1 : std_logic_vector(OP1sz-1 downto 0):=(others => '0'); 00051 signal Operand2 : std_logic_vector(OP2sz-1 downto 0):=(others => '0'); 00052 signal Resultat : std_logic_vector(OP1sz+OP2sz-1 downto 0); 00053 00054 00055 00056 00057 begin 00058 00059 00060 MAC1 : entity LPP_IIR_FILTER.MAC generic map( 00061 Input_SZ_A => OP1sz, 00062 Input_SZ_B => OP2sz 00063 00064 ) 00065 port map( 00066 clk => clk, 00067 reset => reset , 00068 clr_MAC => clrMAC , 00069 MAC_MUL_ADD => MAC_MUL_ADD , 00070 OP1 => Operand1 , 00071 OP2 => Operand2 , 00072 RES => Resultat 00073 ); 00074 00075 clk <= not clk after 25 ns; 00076 00077 process 00078 begin 00079 wait for 40 ns; 00080 reset <= '1'; 00081 wait for 11 ns; 00082 Operand1 <= X"0001"; 00083 Operand2 <= X"001"; 00084 MAC_MUL_ADD <= ADD; 00085 wait for 50 ns; 00086 Operand1 <= X"0001"; 00087 Operand2 <= X"100"; 00088 wait for 50 ns; 00089 Operand1 <= X"0001"; 00090 Operand2 <= X"001"; 00091 MAC_MUL_ADD <= MULT; 00092 wait for 50 ns; 00093 Operand1 <= X"0002"; 00094 Operand2 <= X"002"; 00095 wait for 50 ns; 00096 clrMAC <= '1'; 00097 wait for 50 ns; 00098 clrMAC <= '0'; 00099 Operand1 <= X"0001"; 00100 Operand2 <= X"003"; 00101 MAC_MUL_ADD <= MAC; 00102 wait; 00103 end process; 00104 end ar_TestbenshMAC; 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet