Public Member Functions | Public Attributes

ar_TestbenshMAC Architecture Reference

Inherits MAC.

Inherited by TestbenshMAC.

List of all members.



Processes

PROCESS_13  ( )

Constants

OP1sz  integer := 16
OP2sz  integer := 12
IDLE  std_logic_vector ( 1 downto 0 ) := " 00 "
MAC  std_logic_vector ( 1 downto 0 ) := " 01 "
MULT  std_logic_vector ( 1 downto 0 ) := " 10 "
ADD  std_logic_vector ( 1 downto 0 ) := " 11 "

Signals

clk  std_logic := ' 0 '
reset  std_logic := ' 0 '
clrMAC  std_logic := ' 0 '
MAC_MUL_ADD  std_logic_vector ( 1 downto 0 ) := IDLE
Operand1  std_logic_vector ( OP1sz -1 downto 0 ) := ( others = > ' 0 ' )
Operand2  std_logic_vector ( OP2sz -1 downto 0 ) := ( others = > ' 0 ' )
Resultat  std_logic_vector ( OP1sz +OP2sz -1 downto 0 )

Component Instantiations

MAC1 MAC <Entity MAC>

Detailed Description

Definition at line 34 of file TestbenshMAC.vhd.

Member Function Documentation

PROCESS_13 ( ) [Process]

Definition at line 79 of file TestbenshMAC.vhd.

Member Data Documentation

ADD std_logic_vector ( 1 downto 0 ) := " 11 " [Constant]

Definition at line 44 of file TestbenshMAC.vhd.

clk std_logic := ' 0 ' [Signal]

Reimplemented from MAC.

Definition at line 46 of file TestbenshMAC.vhd.

clrMAC std_logic := ' 0 ' [Signal]

Definition at line 48 of file TestbenshMAC.vhd.

IDLE std_logic_vector ( 1 downto 0 ) := " 00 " [Constant]

Definition at line 41 of file TestbenshMAC.vhd.

MAC std_logic_vector ( 1 downto 0 ) := " 01 " [Constant]

Definition at line 42 of file TestbenshMAC.vhd.

MAC1 MAC [Component Instantiation]

Definition at line 60 of file TestbenshMAC.vhd.

MAC_MUL_ADD std_logic_vector ( 1 downto 0 ) := IDLE [Signal]

Reimplemented from MAC.

Definition at line 49 of file TestbenshMAC.vhd.

MULT std_logic_vector ( 1 downto 0 ) := " 10 " [Constant]

Definition at line 43 of file TestbenshMAC.vhd.

OP1sz integer := 16 [Constant]

Definition at line 38 of file TestbenshMAC.vhd.

OP2sz integer := 12 [Constant]

Definition at line 39 of file TestbenshMAC.vhd.

Operand1 std_logic_vector ( OP1sz -1 downto 0 ) := ( others = > ' 0 ' ) [Signal]

Definition at line 50 of file TestbenshMAC.vhd.

Operand2 std_logic_vector ( OP2sz -1 downto 0 ) := ( others = > ' 0 ' ) [Signal]

Definition at line 51 of file TestbenshMAC.vhd.

reset std_logic := ' 0 ' [Signal]

Reimplemented from MAC.

Definition at line 47 of file TestbenshMAC.vhd.

Resultat std_logic_vector ( OP1sz +OP2sz -1 downto 0 ) [Signal]

Definition at line 52 of file TestbenshMAC.vhd.

The documentation for this class was generated from the following file: