| add | Adder | [Port] |
| clk | Adder | [Port] |
| clr | Adder | [Port] |
| general_purpose | Adder | [Package] |
| IEEE | Adder | [Library] |
| Input_SZ_A | Adder | [Generic] |
| Input_SZ_B | Adder | [Generic] |
| lpp | Adder | [Library] |
| numeric_std | Adder | [Package] |
| OP1 | Adder | [Port] |
| OP2 | Adder | [Port] |
| PROCESS_15(clk, reset) | ar_Adder | [Process] |
| REG | ar_Adder | [Signal] |
| RES | Adder | [Port] |
| RESADD | ar_Adder | [Signal] |
| reset | Adder | [Port] |
| std_logic_1164 | Adder | [Package] |