| BaudGeneration(clk, reset) | ar_BaudGen | [Process] |
| Bclk | BaudGen | [Port] |
| BTrigger | BaudGen | [Port] |
| Capture | BaudGen | [Port] |
| clk | BaudGen | [Port] |
| cpt | ar_BaudGen | [Signal] |
| errorFlag | ar_BaudGen | [Signal] |
| IEEE | BaudGen | [Library] |
| numeric_std | BaudGen | [Package] |
| PROCESS_40(clk) | ar_BaudGen | [Process] |
| reset | BaudGen | [Port] |
| RX_reg | ar_BaudGen | [Signal] |
| RXD | BaudGen | [Port] |
| std_logic_1164 | BaudGen | [Package] |
| triger | ar_BaudGen | [Signal] |