| clk | Clk_divider | [Port] |
| clk_divided | Clk_divider | [Port] |
| clk_int | ar_Clk_divider | [Signal] |
| clk_TRIGER | ar_Clk_divider | [Constant] |
| cpt1 | ar_Clk_divider | [Signal] |
| IEEE | Clk_divider | [Library] |
| OSC_freqHz | Clk_divider | [Generic] |
| PROCESS_17(reset, clk) | ar_Clk_divider | [Process] |
| reset | Clk_divider | [Port] |
| STD_LOGIC_1164 | Clk_divider | [Package] |
| TargetFreq_Hz | Clk_divider | [Generic] |