Programme qui va permettre de générer le signal SYNC. More...
Inherits Gene_SYNC::ar_Gene_SYNC.
Inherited by ar_CNA_TabloC, and lpp_cna [private].
Architectures | |
| ar_Gene_SYNC | Architecture |
Libraries | |
| IEEE | |
Packages | |
| std_logic_1164 | |
| numeric_std | |
Ports | |
| raz | in std_logic |
| Horloge systeme et Reset du composant. | |
| SCLK | in std_logic |
| Horloge systeme et Reset du composant. | |
| enable | in std_logic |
| Autorise ou non l'utilisation du composant. | |
| OKAI_send | out std_logic |
| Flag, Autorise l'envoi (sérialisation) d'une nouvelle donnée. | |
| SYNC | out std_logic |
| Signal de synchronisation du convertisseur généré. | |
Programme qui va permettre de générer le signal SYNC.
Definition at line 28 of file Gene_SYNC.vhd.
enable in std_logic [Port] |
Autorise ou non l'utilisation du composant.
Reimplemented in ar_APB_CNA, and CNA_TabloC.
Definition at line 31 of file Gene_SYNC.vhd.
IEEE library [Library] |
Reimplemented in CNA_TabloC.
Definition at line 22 of file Gene_SYNC.vhd.
numeric_std package [Package] |
Reimplemented in CNA_TabloC.
Definition at line 24 of file Gene_SYNC.vhd.
OKAI_send out std_logic [Port] |
Flag, Autorise l'envoi (sérialisation) d'une nouvelle donnée.
Reimplemented in ar_CNA_TabloC.
Definition at line 32 of file Gene_SYNC.vhd.
raz in std_logic [Port] |
Horloge systeme et Reset du composant.
Reimplemented in ar_CNA_TabloC.
Definition at line 30 of file Gene_SYNC.vhd.
SCLK in std_logic [Port] |
Horloge systeme et Reset du composant.
Reimplemented in APB_CNA, and CNA_TabloC.
Definition at line 30 of file Gene_SYNC.vhd.
std_logic_1164 package [Package] |
Reimplemented in APB_CNA, and CNA_TabloC.
Definition at line 23 of file Gene_SYNC.vhd.
SYNC out std_logic [Port] |
Signal de synchronisation du convertisseur généré.
Reimplemented in APB_CNA, and CNA_TabloC.
Definition at line 33 of file Gene_SYNC.vhd.