RAM_CTRLR2 Entity Reference

Inherits RAM_CTRLR2::ar_RAM_CTRLR2.

Inherited by ar_IIR_CEL_CTRLR, and iir_filter [private].

List of all members.

Architectures
ar_RAM_CTRLR2	Architecture
Libraries
IEEE
lpp
Packages
numeric_std
std_logic_1164
iir_filter	Package <iir_filter>
FILTERcfg	Package <FILTERcfg>
general_purpose	Package <general_purpose>
Generics
Input_SZ_1	integer := 16
Mem_use	integer := use_RAM
Ports
reset	in std_logic
clk	in std_logic
WD_sel	in std_logic
Read	in std_logic
WADDR_sel	in std_logic
count	in std_logic
SVG_ADDR	in std_logic
Write	in std_logic
GO_0	in std_logic
sample_in	in std_logic_vector ( Input_SZ_1 -1 downto 0 )
sample_out	out std_logic_vector ( Input_SZ_1 -1 downto 0 )

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Detailed Description

Definition at line 32 of file RAM_CTRLR2.vhd.

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Member Data Documentation

clk in std_logic [Port]

Reimplemented from REG.

Definition at line 39 of file RAM_CTRLR2.vhd.

count in std_logic [Port]

Definition at line 43 of file RAM_CTRLR2.vhd.

FILTERcfg package [Package]

Definition at line 27 of file RAM_CTRLR2.vhd.

general_purpose package [Package]

Reimplemented from REG.

Definition at line 28 of file RAM_CTRLR2.vhd.

GO_0 in std_logic [Port]

Definition at line 46 of file RAM_CTRLR2.vhd.

IEEE library [Library]

Reimplemented from REG.

Definition at line 22 of file RAM_CTRLR2.vhd.

iir_filter package [Package]

Definition at line 26 of file RAM_CTRLR2.vhd.

Input_SZ_1 integer := 16 [Generic]

Definition at line 34 of file RAM_CTRLR2.vhd.

lpp library [Library]

Reimplemented from REG.

Reimplemented in iir_filter.

Definition at line 25 of file RAM_CTRLR2.vhd.

Mem_use integer := use_RAM [Generic]

Definition at line 35 of file RAM_CTRLR2.vhd.

numeric_std package [Package]

Reimplemented from REG.

Definition at line 23 of file RAM_CTRLR2.vhd.

Read in std_logic [Port]

Definition at line 41 of file RAM_CTRLR2.vhd.

reset in std_logic [Port]

Reimplemented from REG.

Definition at line 38 of file RAM_CTRLR2.vhd.

sample_in in std_logic_vector ( Input_SZ_1 -1 downto 0 ) [Port]

Definition at line 47 of file RAM_CTRLR2.vhd.

sample_out out std_logic_vector ( Input_SZ_1 -1 downto 0 ) [Port]

Definition at line 48 of file RAM_CTRLR2.vhd.

std_logic_1164 package [Package]

Reimplemented from REG.

Reimplemented in iir_filter.

Definition at line 24 of file RAM_CTRLR2.vhd.

SVG_ADDR in std_logic [Port]

Definition at line 44 of file RAM_CTRLR2.vhd.

WADDR_sel in std_logic [Port]

Definition at line 42 of file RAM_CTRLR2.vhd.

WD_sel in std_logic [Port]

Definition at line 40 of file RAM_CTRLR2.vhd.

Write in std_logic [Port]

Definition at line 45 of file RAM_CTRLR2.vhd.

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The documentation for this class was generated from the following file:

• dsp/iir_filter/RAM_CTRLR2.vhd