| clk | Shift_REG | [Port] |
| CptBits | ar_Shift_REG | [Signal] |
| CptBits_flag | ar_Shift_REG | [Signal] |
| CptBits_flag_reg | ar_Shift_REG | [Signal] |
| CptBits_trig | ar_Shift_REG | [Constant] |
| D | Shift_REG | [Port] |
| Data_sz | Shift_REG | [Generic] |
| IEEE | Shift_REG | [Library] |
| numeric_std | Shift_REG | [Package] |
| PROCESS_41(reset, clk) | ar_Shift_REG | [Process] |
| PROCESS_42(reset, Sclk) | ar_Shift_REG | [Process] |
| Q | Shift_REG | [Port] |
| REG | ar_Shift_REG | [Signal] |
| reset | Shift_REG | [Port] |
| Sclk | Shift_REG | [Port] |
| Serial_reg | ar_Shift_REG | [Signal] |
| Serialize | Shift_REG | [Port] |
| Serialize_reg | ar_Shift_REG | [Signal] |
| Serialized | Shift_REG | [Port] |
| Serialized_int | ar_Shift_REG | [Signal] |
| SIN | Shift_REG | [Port] |
| SOUT | Shift_REG | [Port] |
| std_logic_1164 | Shift_REG | [Package] |