Programme de la FIFO. More...
Inherits Top_FifoWrite::ar_Top_FifoWrite.
Inherited by ar_APB_FifoWrite, and lpp_memory [private].
Architectures | |
| ar_Top_FifoWrite | Architecture |
Libraries | |
| IEEE | |
| techmap | |
Packages | |
| std_logic_1164 | |
| numeric_std | |
| gencomp | |
| config | |
Generics | |
| Data_sz | integer := 16 |
| Addr_sz | integer := 8 |
| addr_max_int | integer := 256 |
Ports | |
| raz | in std_logic |
| Horloge et reset general du composant. | |
| clk | in std_logic |
| Horloge et reset general du composant. | |
| flag_RE | in std_logic |
| Flag, Demande la lecture de la mémoire. | |
| flag_WR | in std_logic |
| Flag, Demande l'écriture dans la mémoire. | |
| Data_in | in std_logic_vector ( Data_sz -1 downto 0 ) |
| Data en entrée du composant. | |
| Raddr | in std_logic_vector ( Addr_sz -1 downto 0 ) |
| Adresse du registre d'écriture dans la mémoire. | |
| full | out std_logic |
| Flag, Mémoire pleine. | |
| Waddr | out std_logic_vector ( Addr_sz -1 downto 0 ) |
| Adresse du registre de lecture de la mémoire. | |
| Data_out | out std_logic_vector ( Data_sz -1 downto 0 ) |
| Data en sortie du composant. | |
Programme de la FIFO.
Definition at line 31 of file Top_FifoWrite.vhd.
addr_max_int integer := 256 [Generic] |
Reimplemented from Fifo_Write.
Reimplemented in APB_FifoWrite.
Definition at line 35 of file Top_FifoWrite.vhd.
Addr_sz integer := 8 [Generic] |
Reimplemented from Fifo_Write.
Reimplemented in APB_FifoWrite.
Definition at line 34 of file Top_FifoWrite.vhd.
clk in std_logic [Port] |
Horloge et reset general du composant.
Reimplemented from Fifo_Write.
Reimplemented in APB_FifoWrite.
Definition at line 37 of file Top_FifoWrite.vhd.
config package [Package] |
Definition at line 27 of file Top_FifoWrite.vhd.
Data en entrée du composant.
Definition at line 40 of file Top_FifoWrite.vhd.
Data en sortie du composant.
Definition at line 44 of file Top_FifoWrite.vhd.
Data_sz integer := 16 [Generic] |
Reimplemented in APB_FifoWrite.
Definition at line 33 of file Top_FifoWrite.vhd.
flag_RE in std_logic [Port] |
Flag, Demande la lecture de la mémoire.
Definition at line 38 of file Top_FifoWrite.vhd.
flag_WR in std_logic [Port] |
Flag, Demande l'écriture dans la mémoire.
Reimplemented from Fifo_Write.
Definition at line 39 of file Top_FifoWrite.vhd.
full out std_logic [Port] |
Flag, Mémoire pleine.
Reimplemented from Fifo_Write.
Definition at line 42 of file Top_FifoWrite.vhd.
gencomp package [Package] |
Definition at line 26 of file Top_FifoWrite.vhd.
IEEE library [Library] |
Reimplemented from Fifo_Write.
Definition at line 22 of file Top_FifoWrite.vhd.
numeric_std package [Package] |
Reimplemented from Fifo_Write.
Definition at line 24 of file Top_FifoWrite.vhd.
Adresse du registre d'écriture dans la mémoire.
Reimplemented from Fifo_Write.
Reimplemented in APB_FifoWrite.
Definition at line 41 of file Top_FifoWrite.vhd.
raz in std_logic [Port] |
Horloge et reset general du composant.
Reimplemented from Fifo_Write.
Definition at line 37 of file Top_FifoWrite.vhd.
std_logic_1164 package [Package] |
Reimplemented from Fifo_Write.
Reimplemented in APB_FifoWrite.
Definition at line 23 of file Top_FifoWrite.vhd.
techmap library [Library] |
Definition at line 25 of file Top_FifoWrite.vhd.
Adresse du registre de lecture de la mémoire.
Reimplemented from Fifo_Write.
Definition at line 43 of file Top_FifoWrite.vhd.