00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 library ieee; 00020 use ieee.std_logic_1164.all; 00021 library grlib; 00022 use grlib.amba.all; 00023 -- pragma translate_off 00024 use std.textio.all; 00025 -- pragma translate_on 00026 library lpp; 00027 use lpp.lpp_amba.all; 00028 00029 package lpp_uart is 00030 00031 component UART is 00032 generic(Data_sz : integer := 8); 00033 port( 00034 clk : in std_logic; 00035 reset : in std_logic; 00036 TXD : out std_logic; 00037 RXD : in std_logic; 00038 Capture : in std_logic; 00039 NwDat : out std_logic; 00040 ACK : in std_logic; 00041 Send : in std_logic; 00042 Sended : out std_logic; 00043 BTrigger : out std_logic_vector(11 downto 0); 00044 RDATA : out std_logic_vector(Data_sz-1 downto 0); 00045 WDATA : in std_logic_vector(Data_sz-1 downto 0) 00046 ); 00047 end component; 00048 00049 00050 component Shift_REG is 00051 generic(Data_sz : integer := 10); 00052 port( 00053 clk : in std_logic; 00054 Sclk : in std_logic; 00055 reset : in std_logic; 00056 SIN : in std_logic; 00057 SOUT : out std_logic; 00058 Serialize : in std_logic; 00059 Serialized : out std_logic; 00060 D : in std_logic_vector(Data_sz-1 downto 0); 00061 Q : out std_logic_vector(Data_sz-1 downto 0) 00062 00063 ); 00064 end component; 00065 00066 00067 component BaudGen is 00068 port( 00069 clk : in std_logic; 00070 reset : in std_logic; 00071 Capture : in std_logic; 00072 Bclk : out std_logic; 00073 RXD : in std_logic; 00074 BTrigger : out std_logic_vector(11 downto 0) 00075 ); 00076 end component; 00077 00078 component APB_UART is 00079 generic ( 00080 pindex : integer := 0; 00081 paddr : integer := 0; 00082 pmask : integer := 16#fff#; 00083 pirq : integer := 0; 00084 abits : integer := 8; 00085 Data_sz : integer := 8); 00086 port ( 00087 clk : in std_logic; 00088 rst : in std_logic; 00089 apbi : in apb_slv_in_type; 00090 apbo : out apb_slv_out_type; 00091 TXD : out std_logic; 00092 RXD : in std_logic 00093 ); 00094 end component; 00095 00096 00097 end lpp_uart;
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet