00001 ------------------------------------------------------------------------------ 00002 -- This file is a part of the LPP VHDL IP LIBRARY 00003 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS 00004 -- 00005 -- This program is free software; you can redistribute it and/or modify 00006 -- it under the terms of the GNU General Public License as published by 00007 -- the Free Software Foundation; either version 3 of the License, or 00008 -- (at your option) any later version. 00009 -- 00010 -- This program is distributed in the hope that it will be useful, 00011 -- but WITHOUT ANY WARRANTY; without even the implied warranty of 00012 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00013 -- GNU General Public License for more details. 00014 -- 00015 -- You should have received a copy of the GNU General Public License 00016 -- along with this program; if not, write to the Free Software 00017 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00018 ------------------------------------------------------------------------------- 00019 -- Author : Alexis Jeandet 00020 -- Mail : alexis.jeandet@lpp.polytechnique.fr 00021 ---------------------------------------------------------------------------- 00022 library IEEE; 00023 use IEEE.numeric_std.all; 00024 use IEEE.std_logic_1164.all; 00025 library lpp; 00026 use lpp.lpp_uart.all; 00027 00031 00032 entity UART is 00033 generic(Data_sz : integer := 8); 00034 port( 00035 clk : in std_logic; 00036 reset : in std_logic; 00037 TXD : out std_logic; 00038 RXD : in std_logic; 00039 Capture : in std_logic; 00040 NwDat : out std_logic; 00041 ACK : in std_logic; 00042 Send : in std_logic; 00043 Sended : out std_logic; 00044 BTrigger : out std_logic_vector(11 downto 0); 00045 RDATA : out std_logic_vector(Data_sz-1 downto 0); 00046 WDATA : in std_logic_vector(Data_sz-1 downto 0) 00047 ); 00048 end entity; 00049 00050 00051 architecture ar_UART of UART is 00052 signal Bclk : std_logic; 00053 00054 signal RDATA_int : std_logic_vector(Data_sz+1 downto 0); 00055 signal WDATA_int : std_logic_vector(Data_sz+1 downto 0); 00056 00057 signal TXD_Dummy : std_logic; 00058 signal NwDat_int : std_logic; 00059 signal NwDat_int_reg : std_logic; 00060 signal receive : std_logic; 00061 constant zeroVect : std_logic_vector(Data_sz+1 downto 0) := (others => '0'); 00062 00063 begin 00064 00065 00066 00067 WDATA_int <= '1' & WDATA & '0'; 00068 00069 BaudGenerator : entity work.BaudGen port map(clk,reset,Capture,Bclk,RXD,BTrigger); 00070 00071 00072 RX_REG : entity work.Shift_REG generic map(Data_sz+2) 00073 port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,zeroVect,RDATA_int); 00074 00075 TX_REG : entity work.Shift_REG generic map(Data_sz+2) 00076 port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int); 00077 00078 00079 00080 process(clk,reset) 00081 begin 00082 if reset = '0' then 00083 NwDat <= '0'; 00084 elsif clk'event and clk = '1' then 00085 NwDat_int_reg <= NwDat_int; 00086 if RXD = '1' and NwDat_int = '1' then 00087 receive <= '0'; 00088 elsif RXD = '0' then 00089 receive <= '1'; 00090 end if; 00091 if NwDat_int_reg = '0' and NwDat_int = '1' then 00092 NwDat <= '1'; 00093 RDATA <= RDATA_int(8 downto 1); 00094 elsif ack = '1' then 00095 NwDat <= '0'; 00096 end if; 00097 end if; 00098 end process; 00099 00100 end ar_UART; 00101 00102 00103 00104
© Copyright 2011 LPP-CNRS | Design by Alexis Jeandet